Laser Bonding for Stacking Semiconductor Substrates

• US 20100178732A1
• Filed: 11/13/2009
• Published: 07/15/2010
• Est. Priority Date: 01/14/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Jung-Huei, Wu, Ting-Hau, Lee, Jiou-Kang, Cheng, Chun-Ren, Tsai, Shang-Ying
• Granted Patent: US 8,367,516 B2
• Time in Patent Office: Days
• US Class Current: 438/109
• CPC Class Codes: B23K 26/24 Seam welding
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/484 Connecting portions
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/85 using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

Methods and structures using laser bonding for stacking semiconductor substrates are described. In one embodiment, a method of forming a semiconductor device includes forming a trench in a first substrate, and a bond pad on a second substrate comprising active circuitry. A top surface of the bond pad includes a first material. The first substrate is aligned over the second substrate to align the trench over the bond pad. An electromagnetic beam is directed into the trench to form a bond between the first material on the bond pad and a second material at a bottom surface of the first substrate.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a trench in a first substrate;

forming a bond pad on a second substrate comprising active circuitry, a top surface of the bond pad comprising a first material;

aligning the first substrate over the second substrate, wherein the trench is aligned over the bond pad; and

directing a radiative beam into the trench to form a bond between the first material on the bond pad and a second material at a bottom surface of the first substrate.

2. The method of claim 1, wherein the first material is selected from the group consisting of gold, silver, aluminum, tin, and lead.

3. The method of claim 1, wherein the second material comprises silicon or germanium.

4. The method of claim 1, wherein forming the bond comprises forming a eutectic alloy of the first material and the second material.

5. The method of claim 1, further comprising depositing the second material into the trench, wherein the trench comprises a through substrate trench.

6. The method of claim 5, wherein the second material is selected from the group consisting of silicon, germanium, gold, silver, aluminum, tin, and lead.

7. The method of claim 1, wherein the bond between the first material on the bond pad and the second material on the first substrate is electrically conductive.

8. The method of claim 1, further comprising depositing a heat absorbing material over the trench before directing the radiative beam.

9. The method of claim 8, wherein the heat absorbing material comprises carbon.

10. The method of claim 1, wherein the first substrate comprises a semiconductor wafer with electrical circuitry.

11. The method of claim 1, further comprising stacking a third substrate over the first substrate, and electrically coupling the third substrate to the second substrate through the trench and the bond pad, wherein the third substrate comprises electrical circuitry.

12. The method of claim 11, wherein the electrical coupling uses wire bonds.

13. The method of claim 1, wherein the radiative beam comprises an electromagnetic beam.

14. The method of claim 1, wherein the radiative beam comprises an electromagnetic laser beam.

15. The method of claim 14, wherein a wavelength of the laser beam is less than about 648 nm, and wherein the speed of the laser beam relative to the first substrate is greater than about 100 mm/sec.

16. The method of claim 1, wherein the radiative beam is not directed between adjacent trenches of the first substrate.

17. A method of forming a semiconductor device, the method comprising:

forming a first row and a second row of vias in a first substrate;

forming first and a second row of bond pads on a second substrate comprising active circuitry;

aligning the first substrate over the second substrate, wherein the first row of vias are aligned over the first row of bond pads, and wherein the second row of vias are aligned over the second row of bond pads; and

directing a photon beam over the first and second rows of vias to form a conductive bond between a first material on the bond pads and a second material at a bottom surface of the first row and the second row of vias.

18. The method of claim 17, further comprising depositing the second material into the first and the second rows of vias, wherein the first and the second rows of vias comprise through substrate vias.

19. The method of claim 18, further comprising depositing a heat absorbing material over the first and the second rows of vias, the heat absorbing material being disposed over the second material before directing the photon beam.

20. The method of claim 17, wherein the photon beam is a laser beam.

21. The method of claim 20, wherein a wavelength of the laser beam is less than about 648 nm, and wherein the speed of the laser beam relative to the first substrate is greater than about 100 mm/sec.

22. The method of claim 20, wherein a spot beam width of the laser beam is less than the distance between the first row of vias and the second row of vias.

23. The method of claim 20, wherein the laser beam is sequentially scanned over the first row of vias and then over the second row of vias.

24. The method of claim 17, wherein the photon beam is not directed between adjacent vias of the first substrate.