Method of fabricating nonvolatile memory device

• US 20100178755A1
• Filed: 01/13/2010
• Published: 07/15/2010
• Est. Priority Date: 01/14/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Youngok, Bae, Sang Won, Lee, Hyosan, Kang, Daehyuk, Kim, Young-Hoo, Yoon, Boun, Kim, Donghyun, Lee, Kuntack, Park, Imsoo
• Granted Patent: US 8,076,198 B2
• Time in Patent Office: Days
• US Class Current: 438/479
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

A method of fabricating a nonvolatile memory device with a three-dimensional structure includes alternately stacking first and second material layers in two or more layers on a semiconductor substrate, forming trenches penetrating the stacked first and second material layers by performing a first etching process, and removing the second material layers exposed in the trenches by performing a second etching process. The first and second material layers are formed of materials that have the same main component but have different impurity contents, respectively.

Claims

1. A method of fabricating a nonvolatile memory device, the method comprising:

alternately stacking first and second material layers in two or more layers on a semiconductor substrate;

forming trenches penetrating the stacked first and second material layers by performing a first etching process; and

removing the second material layers exposed in the trenches by performing a second etching process,

wherein the first and second material layers are formed of materials that have the same main component and have different impurity contents, respectively.

2. The method as set forth in claim 1, wherein an etch selectivity of the first and second material layers during the second etching process is greater than that of the first and second material layers during the first etching process.

3. The method as set forth in claim 2, wherein an etch rate of the second material layer is greater than that of the first material layer during the second etching process.

4. The method as set forth in claim 1, wherein the first and second material layers are stacked in-situ.

5. The method as set forth in claim 1, wherein the first and second material layers are formed of a silicon oxide, and

the impurity content of the second material layer is greater than that of the first material layer.

6. The method as set forth in claim 5, wherein the first material layer is formed of a thermal oxide, TEOS (Tetra Ethyl Ortho Silicate), HDP (High Density Plasma), or USG (Undoped Silicate Glass), and

the second material layer is formed of BPSG (BoroPhosphoSilicate Glass), BSG (BoroSilicate Glass), or PSG (PhosphoSilicate Glass).

7. The method as set forth in claim 6, wherein the second etching process removes the second material layer by using HF gas, mixtures of hydrofluoric acid and de-ionized water, or mixtures of low-polar organic solvent, hydrofluoric acid, and de-ionized water.

8. The method as set forth in claim 1, wherein the first etching process is an anisotropic etching process, and the second etching process is an isotropic etching process.

9. The method as set forth in claim 1, wherein the forming of the trenches includes forming a first trench and forming a second trench after forming the first trench, and

wherein the method further includes forming a semiconductor pattern at an inner wall of the first trench after forming the first trench.

10. The method as set forth in claim 9, wherein the removing of the second material layers includes removing the second material layers exposed by the second trench and exposing portions of sidewalls of the semiconductor pattern, and

wherein the method further includes forming a charge storage layer and a conductive pattern on the exposed semiconductor pattern.