Matrix microprocessor and method of operation
First Claim
1. A microprocessor, comprising:
- a direct memory access (DMA) engine responsive to one or more pairs of block indices associated with one or more blocks in a first logical plane and operative to transfer the one or more blocks, to/from at least one of the first logical plane, a second logical plane, and a physical memory space according to the one or more pairs of block indices.
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Accused Products
Abstract
A microprocessor includes a direct access memory (DMA) engine which is responsive to pairs of block indices associated with one or more blocks in a first logical plane and transfers the one or more blocks between the first logical plane, a second logical plane, and a physical memory space according to the pairs of block indices. The logical planes represent two dimensional fields of data such as those found in images and videos. The microprocessor further comprises cache memory which updates its content with one or more cache-blocks which are in the neighborhood of the one or more blocks improving the operation of the cache memory by increasing cache hits. The DMA engine may further operate on n-dimensional blocks in a n-dimensional logical space. The microprocessor further includes special-purpose instructions, operative on a single-instruction-multiple-data (SIMD) computation unit, especially tailored to perform matrix operations. The SIMD may share scalar operands with an onboard single-instruction-single-data (SISD) computation unit.
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Citations
42 Claims
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1. A microprocessor, comprising:
a direct memory access (DMA) engine responsive to one or more pairs of block indices associated with one or more blocks in a first logical plane and operative to transfer the one or more blocks, to/from at least one of the first logical plane, a second logical plane, and a physical memory space according to the one or more pairs of block indices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A microprocessor, comprising:
a direct memory access (DMA) engine responsive to one or more n-dimensional block indices associated with one or more n-dimensional blocks in a first n-dimensional logical space and operative to transfer the one or more n-dimensional blocks, to/from at least one of the first n-dimensional logical space, a second n-dimensional logical space, and a physical memory space according to the one or more n-dimensional block indices, wherein n is greater than two. - View Dependent Claims (30, 31, 32)
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33. A method of processing data via a microprocessor, comprising:
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(a) providing a direct memory access (DMA) engine responsive to one or more pairs of block indices associated with one or more blocks in a first logical plane; and (b) transferring the one or more blocks, to/from at least one of the first logical plane, a second logical plane, and a physical memory space according to the one or more pairs of block indices, via the DMA engine. - View Dependent Claims (34, 35, 36, 37, 38)
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39. A method of processing data via a microprocessor, comprising:
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(a) providing a direct memory access (DMA) engine responsive to one or more n-dimensional block indices associated with one or more n-dimensional blocks in a first n-dimensional logical space; and (b) transferring the one or more n-dimensional blocks, to/from at least one of the first n-dimensional logical space, a second n-dimensional logical space, and a physical memory space according to the one or more n-dimensional block indices, via the DMA engine, wherein n is greater than two. - View Dependent Claims (40, 41, 42)
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Specification