CIRCUIT FOR REDUCING THE READ DISTURBANCE IN MEMORY

• US 20100180183A1
• Filed: 01/12/2009
• Published: 07/15/2010
• Est. Priority Date: 01/12/2009
• Status: Abandoned Application

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Hung, Chun-Hsiung, Hung, Shuo-Nan
• Application Number:
  US12/351,984
• Publication Number:
  US 20100180183A1
• Time in Patent Office: Days
• US Class Current: 714/807
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A memory includes an internal data block and a temporary storing unit. The internal data block stores internal data of the memory. The temporary storing unit temporarily stores the internal data of the memory after the memory is powered on.

Claims

1. A memory, comprising:

an internal data block for storing internal data of the memory; and

a temporary storing unit for temporarily storing the internal data of the memory after the memory is powered on.

2. The memory according to claim 1, wherein the internal data comprises chip parameter information of the memory.

3. The memory according to claim 2, wherein the internal data comprises security information of the memory.

4. The memory according to claim 1, wherein the memory further comprises a main memory block, and the memory is verified according to the internal data temporarily stored in the temporary storing unit after the memory is powered on so that an external host can access the main memory block.

5. The memory according to claim 1, wherein the temporary storing unit is a static random access memory or a register.

6. The memory according to claim 1, wherein the internal data block further stores an error correction code, and the memory further comprises an error correction circuit for making the memory correctly read the internal data according to the error correction code.

7. The memory according to claim 1, wherein the internal data is stored in the internal data block with a format of a single level unit (SLC), and at least two rows of memory cells of the internal data block store the same internal data.

8. A memory, comprising:

an internal data block for storing internal data of the memory and an error correction code; and

an error correction circuit for making the memory correctly read the internal data according to the error correction code.

9. The memory according to claim 8, wherein the internal data comprises chip parameter information of the memory.

10. The memory according to claim 9, wherein the internal data comprises security information of the memory.

11. The memory according to claim 8, further comprising a main memory block, wherein the internal data are corrected according to the error correction code after the memory is powered on so that an external host can access the main memory block according to the verification with the internal data.

12. The memory according to claim 8, wherein the internal data and the error correction code are stored in the internal data block with a format of a single level unit, and at least two rows of memory cells of the internal data block store the same internal data and the error correction code.

13. A memory, comprising:

a main memory block; and

an internal data block for storing internal data of the memory, wherein at least two rows of memory cells of the internal data block store the same internal data,

wherein the memory is verified according to the internal data after the memory is powered on so that an external host can access the main memory block.

14. The memory according to claim 13, wherein the internal data comprises chip parameter information or security information of the memory.

15. The memory according to claim 14, wherein the internal data comprises security information of the memory.

16. The memory according to claim 13, wherein the main memory block stores data with a format of a multi-level unit.

17. The memory according to claim 13, wherein when the memory reads the internal data, a low pass voltage is applied to a word line corresponding to a memory cell of the internal data block, which is not read.

18. The memory according to claim 17, wherein the low pass voltage is between a read voltage and a low bound of high threshold voltage distribution.

19. The memory according to claim 13, wherein the memory cells of the same bit line of the internal data block storing the same data.