Semiconductor Device
First Claim
1. A semiconductor device comprising:
- a first transistor;
a second transistor;
a third transistor;
a capacitor; and
a buffer,wherein one of a source and a drain of the second transistor is electrically connected to an input terminal,wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the third transistor,wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor and an input of the buffer,wherein the other electrode of the capacitor is electrically connected to a reference voltage terminal, andwherein an output of the buffer is electrically connected to an output terminal and the other of the source and the drain of the third transistor.
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Accused Products
Abstract
A semiconductor device which stores data, and in which refresh operation is not needed, is described. The semiconductor device comprises at least a transistor and a capacitor. A first electrode of the capacitor is connected to a reference voltage terminal and a second electrode of the capacitor is connected to one of a source and a drain of the transistor. The semiconductor device is configured to put, when necessary, the other of the source and the drain of the transistor to the same potential as the one of the source and the drain, so that charge accumulated in the capacitor, which is connected to the one of the source and the drain of the transistor, does not leak through the transistor.
42 Citations
14 Claims
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1. A semiconductor device comprising:
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a first transistor; a second transistor; a third transistor; a capacitor; and a buffer, wherein one of a source and a drain of the second transistor is electrically connected to an input terminal, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the third transistor, wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor and an input of the buffer, wherein the other electrode of the capacitor is electrically connected to a reference voltage terminal, and wherein an output of the buffer is electrically connected to an output terminal and the other of the source and the drain of the third transistor. - View Dependent Claims (2, 3)
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4. A semiconductor device comprising:
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a first inverter; a second inverter; a transistor; a capacitor; a buffer; a first analog switch; a second analog switch; a first input terminal; a second input terminal; and an output terminal, wherein the first input terminal is electrically connected to an input of the first inverter, wherein an output of the first inverter is electrically connected to an input of the second inverter, a second control terminal of the first analog switch, and a first control terminal of the second analog switch, wherein an output of the second inverter is electrically connected to a first control terminal of the first analog switch, a second control terminal of the second analog switch, and a gate of the transistor, wherein the second input terminal is electrically connected to an input of the first analog switch, wherein an output of the first analog switch is electrically connected to one of a source and a drain of first transistor and to an output of the second analog switch, wherein the other of the source and the drain of the transistor is electrically connected to an electrode of the capacitor and an input of the buffer, wherein the other electrode of the capacitor is electrically connected to a reference voltage terminal, and wherein an output of the buffer is electrically connected to the output terminal and to an input of the second analog switch. - View Dependent Claims (5, 6)
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7. A semiconductor device comprising:
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an antenna; a rectifier circuit; a logic portion; and a flag holding circuit, wherein the logic portion includes a clock circuit, a logic circuit, a demodulation circuit, and a modulation circuit, wherein the flag holding circuit includes a first transistor, a second transistor, a third transistor, a capacitor, and a buffer, wherein the antenna is connected to the rectifier circuit, wherein the rectifier circuit is connected to the logic portion and the flag holding circuit, wherein a gate of the second transistor is electrically connected to the logic circuit, one of a source and a drain of the second transistor is electrically connected to an input terminal, and the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the third transistor, wherein a gate of the first transistor is electrically connected to the logic circuit, and the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor and an input of the buffer, wherein the other electrode of the capacitor is electrically connected to a reference voltage terminal, wherein an output of the buffer is electrically connected to an output terminal and the other of the source and the drain of the third transistor, and wherein a gate of the third transistor is electrically connected to the logic circuit. - View Dependent Claims (8, 9, 10)
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11. A semiconductor device comprising:
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an antenna; a rectifier circuit; a logic portion; and a flag holding circuit, wherein the antenna is connected to the rectifier circuit and to the logic portion, wherein the rectifier circuit is connected to the logic portion and the flag holding circuit, wherein a logic portion includes a clock circuit, a logic circuit, a demodulation circuit, and a modulation circuit; and wherein a flag holding circuit includes a first inverter, a second inverter, a transistor, a capacitor, a buffer, a first analog switch, a second analog switch, a first input terminal, a second input terminal, and an output terminal, wherein the logic portion is electrically connected to the second input terminal, wherein the first input terminal is electrically connected to an input of the first inverter, wherein an output of the first inverter is electrically connected to an input of the second inverter, a second control terminal of the first analog switch, and a first control terminal of the second analog switch, wherein an output of the second inverter is electrically connected to a first control terminal of the first analog switch, a second control terminal of the second analog switch, and a gate of the first transistor, wherein the second input terminal is electrically connected to an input of the first analog switch, wherein an output of the first analog switch is electrically connected to one of a source and a drain of the transistor and to an output of the second analog switch, wherein the other of the source and the drain of the transistor is electrically connected to an electrode of the capacitor and to an input of the buffer, wherein the other electrode of the capacitor is electrically connected to a reference voltage terminal, and wherein an output of the buffer is electrically connected to the output terminal and an input of the second analog switch. - View Dependent Claims (12, 13, 14)
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Specification