LASER LIFT-OFF WITH IMPROVED LIGHT EXTRACTION

• US 20100181584A1
• Filed: 07/11/2006
• Published: 07/22/2010
• Est. Priority Date: 07/11/2005
• Status: Abandoned Application

• Current Assignee: Lumination LLC
• Original Assignee: Lumination LLC
• Inventors: Venugopalan, Hari S., Sackrison, Michael, Eliashevich, Ivan, Gao, Xiang
• Application Number:
  US12/304,533
• Publication Number:
  US 20100181584A1
• Time in Patent Office: Days
• US Class Current: 257/98
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2933/0091 Scattering means in or on the semiconductor body or semiconductor body package H01L33/22 takes precedence
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01L 33/64 Heat extraction or cooling elements

Abstract

A light emitting device includes a stack of semiconductor layers defining a light emitting pn junction and a dielectric layer disposed over the stack of semiconductor layers. The dielectric layer has a refractive index substantially matching a refractive index of the stack of semiconductor layers. The dielectric layer has a principal surface distal from the stack of semiconductor layers. The distal principal surface includes patterning, roughening, or texturing configured to promote extraction of light generated in the stack of semiconductor layers.

Claims

1. A light emitting device comprising:

a stack of semiconductor layers defining a light-emitting pn junction; and

a dielectric layer disposed over the stack of semiconductor layers, the dielectric layer having a refractive index substantially matching a refractive index of the stack of semiconductor layers, the dielectric layer having a principal surface distal from the stack of semiconductor layers, the distal principal surface including patterning, roughening, or texturing configured to promote extraction of light generated in the stack of semiconductor layers.

2. The lighting emitting device as set forth in claim 1, further comprising:

a host substrate or sub-mount on which is disposed the stack of semiconductor layers, the host substrate or sub-mount being different from a deposition substrate on which the stack of semiconductor layers was formed.

3. The light emitting device as set forth in claim 2, wherein the host substrate or sub-mount includes bonding bumps electrically connecting with the stack of semiconductor layers to enable electrical energizing of the light-emitting pn junction.

4. The light emitting device as set forth in claim 2, wherein the host substrate or sub-mount is a silicon substrate or sub-mount.

5. The light emitting device as set forth in claim 2, wherein the stack of semiconductor layers have first and second opposite principal surfaces, the second principal surface being secured to the host substrate, the first principal surface having been secured to the deposition substrate during formation of the stack of semiconductor layers on the deposition substrate.

6. The light emitting device as set forth in claim 1, wherein the light-emitting pn junction includes a multi-quantum well region.

7. The light emitting device as set forth in claim 1, wherein the stack of semiconductor layers include semiconductor layers selected from a group consisting of:

a gallium nitride (GaN) layer, an aluminum nitride (AlN) layer, an indium nitride (InN) layer, layers comprising ternary alloys of GaN, AlN, or InN, and layers comprising quaternary alloys of GaN, AlN, and InN.

8. The light emitting device as set forth in claim 7, wherein the light-emitting pn junction includes a multi-quantum well region including a plurality of layers containing InN or alloys thereof.

9. The light emitting device as set forth in claim 1, wherein the dielectric layer does not completely cover the stack of semiconductor layers, the patterning, roughening, or texturing of the distal principal surface being defined by the incomplete coverage of the stack of semiconductor layers.

10. The light emitting device as set forth in claim 1, wherein the dielectric layer includes openings exposing the underlying stack of semiconductor layers, the openings defining the patterning, roughening, or texturing of the distal principal surface.

11. The light emitting device as set forth in claim 1, wherein the dielectric layer has a proximate principal surface contacting the stack of semiconductor layers, the proximate principal surface contacting the stack of semiconductor layers not including the patterning, roughening, or texturing of the distal principal surface.

12. The light emitting device as set forth in claim 1, wherein the patterning, roughening, or texturing of the distal principal surface includes at least one lateral periodicity.

13. The light emitting device as set forth in claim 1, wherein the patterning, roughening, or texturing of the distal principal surface is substantially random and non-periodic.

14. The light emitting device as set forth in claim 1, wherein the patterning, roughening, or texturing defines microlenses.

15. The light emitting device as set forth in claim 1, wherein the patterning, roughening, or texturing biases extracted light toward a selected viewing angle.

16. The light emitting device as set forth in claim 1, further comprising:

an anti-reflection coating disposed on the distal principal surface of the dielectric layer.

17. A method for fabricating a light emitting device, the method comprising:

forming a stack of semiconductor layers defining a light-emitting pn junction; and

disposing a dielectric layer over the stack of semiconductor layers, the dielectric layer having a refractive index substantially matching a refractive index of the stack of semiconductor layers, the dielectric layer having a principal surface distal from the stack of semiconductor layers, the distal principal surface including patterning, roughening, or texturing configured to promote extraction of light generated in the stack of semiconductor layers.

18. The method as set forth in claim 17, wherein the forming comprises:

depositing the stack of semiconductor layers on a deposition substrate.

19. The method as set forth in claim 18, wherein the forming further comprises:

transferring the stack of semiconductor layers from the deposition substrate to a host substrate or sub-mount.

20. The method as set forth in claim 19, wherein the transferring comprises:

detaching the stack of semiconductor layers from the deposition substrate by a laser lift-off process.

21. The method as set forth in claim 19, wherein the transferring comprises:

attaching a second principal surface of the stack of semiconductor layers to the host substrate or sub-mount; and

detaching a first principal surface opposite the second principal surface from the deposition substrate.

22. The method as set forth in claim 21, wherein the detaching comprises:

applying a laser beam to the deposition substrate to the deposition substrate, the laser beam passing through the deposition substrate substantially unattenuated and being absorbed proximate to the first principal surface of the stack of semiconductor layers.

23. The method as set forth in claim 21, wherein the attaching comprises:

attaching the second principal surface of the stack of semiconductor layers to bonding bumps of the host substrate or sub-mount, the bonding effectuating electrical connection of at least some of the bonding bumps with the stack of semiconductor layers to enable electrical energizing of the light-emitting pn junction.

24. The method as set forth in claim 17 wherein the forming comprises:

forming the stack of semiconductor layers including semiconductor layers selected from a group consisting of;

a gallium nitride (GaN) layer, an aluminum nitride (AlN) layer, an indium nitride (InN) layer, layers comprising ternary alloys of GaN, AlN, or InN, and layers comprising quaternary alloys of GaN, AlN, and InN.

25. The method as set forth in claim 17, wherein the forming comprises:

forming the pn junction including a multi-quantum well region.

26. The method as set forth in claim 17, wherein the disposing of the dielectric layer over the stack of semiconductor layers comprises:

forming the patterning, roughening, or texturing into the distal principal surface after the disposing of the dielectric layer.

27. The method as set forth in claim 26, wherein the forming of the patterning, roughening, or texturing comprises:

etching away selected portions of the disposed dielectric layer.

28. The method as set forth in claim 27, wherein the selected portions extend to the underlying stack of semiconductor layers to define openings in the disposed dielectric layer.

29. The method as set forth in claim 27, wherein the selected portions do not extend to the underlying stack of semiconductor layers.

30. The method as set forth in claim 27,wherein the selected portions are defined by a mask.

31. The method as set forth in claim 27, wherein the forming of the patterning, roughening, or texturing into the distal principal surface further comprises:

disposing polystyrene members on the disposed dielectric layer, the disposed polystyrene members defining the selected portions.

32. The method as set forth in claim 17, wherein the disposing of the dielectric layer over the stack of semiconductor layers comprises:

disposing the dielectric layer using a lift-off patterning process that defines the patterning, roughening, or texturing.

33. A light emitting device comprising:

a stack of semiconductor layers defining a light-emitting pn junction;

a host substrate or sub-mount on which is disposed the stack of semiconductor layers, the host substrate or sub-mount being different from a deposition substrate on which the stack of semiconductor layers was formed; and

patterning, roughening, or texturing configured to promote extraction of light generated in the stack of semiconductor layers formed on a distal principal surface of the stack of semiconductor layers that is distal from the host substrate or sub-mount.

34. The lighting emitting device as set forth in claim 33, further comprising:

a dielectric layer disposed over the distal principal surface of the stack of semiconductor layers, the dielectric layer having a refractive index substantially matching a refractive index of the stack of semiconductor layers.

35. A method for fabricating a light emitting device, the method comprising:

forming a stack of semiconductor layers defining a light-emitting pn junction on a deposition substrate;

transferring the formed stack of semiconductor layers from the deposition substrate to a host substrate or sub-mount, the transferring exposing a new principal surface of the stack of semiconductor layers that was not exposed when the stack of semiconductor layers was formed on the deposition substrate; and

generating patterning, roughening, or texturing configured to promote extraction of light generated in the stack of semiconductor layers on the new principal surface of the stack of semiconductor layers.

36. The method as set forth in claim 35, wherein the transferring comprises:

detaching the stack of semiconductor layers from the deposition substrate using a laser lift-off process.

37. The method as set forth in claim 35, further comprising:

disposing a dielectric layer disposed on the new principal surface including on the patterning, roughening, or texturing.