CHIP PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME
First Claim
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1. A chip package structure, comprising:
- a carrier substrate having a cavity;
a plurality of isolated conductive layers disposed on the carrier substrate;
at least one chip disposed in the cavity of the carrier substrate, wherein the chip has a plurality of electrodes to electrically connect to the conductive layers; and
a conductive path disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminated holes.
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Abstract
The invention provides a chip package structure and method for fabricating the same. The chip package structure includes a carrier substrate. A plurality of isolated conductive layers is disposed on the carrier substrate. At least one chip is disposed on the carrier substrate, wherein the chip has a plurality of electrodes. The electrodes are electrically connected to the conductive layers. A conductive path is disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminating holes.
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Citations
20 Claims
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1. A chip package structure, comprising:
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a carrier substrate having a cavity; a plurality of isolated conductive layers disposed on the carrier substrate; at least one chip disposed in the cavity of the carrier substrate, wherein the chip has a plurality of electrodes to electrically connect to the conductive layers; and a conductive path disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminated holes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for fabricating a chip package structure, comprising:
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providing a carrier substrate; forming a first hole from a first surface of the carrier substrate; forming a second hole from a second surface of the carrier substrate, connected and disposed corresponding to the first hole; forming a cavity on the second surface of the carrier substrate; forming a conductive path in the first hole and the second hole and forming a plurality of conductive layers isolated from each other, electrically connected to the conductive path; and disposing at least one chip in the cavity of the carrier substrate, wherein the chip has a plurality of electrodes to electrically connect to the conductive layers. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification