CHIP PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME

• US 20100181589A1
• Filed: 12/11/2009
• Published: 07/22/2010
• Est. Priority Date: 12/11/2008
• Status: Abandoned Application

• Current Assignee: Xintec Incorporated
• Original Assignee: Xintec Incorporated
• Inventors: HUANG, Tien-Hao, TSAI, Chia-Lun, WU, Shang-Yi
• Application Number:
  US12/636,657
• Publication Number:
  US 20100181589A1
• Time in Patent Office: Days
• US Class Current: 257/98
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01L 33/642 characterized by the shape
• CPC Class Codes: H01L 33/647 the elements conducting electric current to or from the semiconductor body

Abstract

The invention provides a chip package structure and method for fabricating the same. The chip package structure includes a carrier substrate. A plurality of isolated conductive layers is disposed on the carrier substrate. At least one chip is disposed on the carrier substrate, wherein the chip has a plurality of electrodes. The electrodes are electrically connected to the conductive layers. A conductive path is disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminating holes.

Claims

1. A chip package structure, comprising:

a carrier substrate having a cavity;

a plurality of isolated conductive layers disposed on the carrier substrate;

at least one chip disposed in the cavity of the carrier substrate, wherein the chip has a plurality of electrodes to electrically connect to the conductive layers; and

a conductive path disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminated holes.

2. The chip package structure as claimed in claim 1, further comprising an insulating layer isolating the conductive layers and the carrier substrate or the conductive path and the carrier substrate from each other.

3. The chip package structure as claimed in claim 1, wherein the conductive layers are conformably disposed on sidewalls and a bottom portion of the cavity.

4. The chip package structure as claimed in claim 1, wherein the carrier substrate is a silicon substrate.

5. The chip package structure as claimed in claim 1, further comprising a reflection layer disposed on sidewalls and a bottom portion of the cavity.

6. The chip package structure as claimed in claim 1, wherein the conductive path passes through the carrier substrate.

7. The chip package structure as claimed in claim 6, wherein the conductive path comprises a plurality of vertically laminated holes and the conductive layers extend on a sidewall of the cavity.

8. The chip package structure as claimed in claim 7, wherein a plurality of the vertically laminated holes comprises a first hole and a second hole, wherein the first hole and the second hole comprise a lateral conductive plate therebetween, wherein the lateral conductive plate electrically connects to the conductive layers extended on the sidewall of the cavity.

9. The chip package structure as claimed in claim 7, wherein a plurality of the vertically laminated holes comprises a first hole and a second hole, wherein a surface of the first hole adjacent to the second hole is larger than a surface of the second hole adjacent to the first hole.

10. The chip package structure as claimed in claim 7, wherein a plurality of the vertically laminated holes comprises a first hole and a second hole, wherein a surface of the first hole adjacent to the second hole is larger than a surface of the second hole adjacent to the first hole, wherein the first hole and the second hole comprise a lateral conductive plate therebetween, wherein the lateral conductive plate electrically connects to the conductive layers extending on the sidewall of the cavity.

11. The chip package structure as claimed in claim 10, wherein the first hole is a lower-level hole and the second hole is an upper-level hole.

12. The chip package structure as claimed in claim 11, wherein a depth of the upper-level hole is the same to that of the cavity.

13. A method for fabricating a chip package structure, comprising:

providing a carrier substrate;

forming a first hole from a first surface of the carrier substrate;

forming a second hole from a second surface of the carrier substrate, connected and disposed corresponding to the first hole;

forming a cavity on the second surface of the carrier substrate;

forming a conductive path in the first hole and the second hole and forming a plurality of conductive layers isolated from each other, electrically connected to the conductive path; and

disposing at least one chip in the cavity of the carrier substrate, wherein the chip has a plurality of electrodes to electrically connect to the conductive layers.

14. The method for fabricating a chip package structure as claimed in claim 13, further comprising forming an insulating layer on the carrier substrate to isolate the conductive layers from the conductive path.

15. The method for fabricating a chip package structure as claimed in claim 14, wherein the first hole and the second hole comprise a lateral conductive plate therebetween.

16. The method for fabricating a chip package structure as claimed in claim 14, wherein a surface of the first hole adjacent to the second hole is larger than a surface of the second hole adjacent to the first hole.

17. The method for fabricating a chip package structure as claimed in claim 14, wherein the first hole and the second hole comprise a lateral conductive plate therebetween, and a surface of the first hole adjacent to the second hole is larger than a surface of the second hole adjacent to the first hole.

18. The method for fabricating a chip package structure as claimed in claim 14, wherein the first hole is a lower-level hole and the second hole is an upper-level hole.

19. The method for fabricating a chip package structure as claimed in claim 18, wherein the upper-level hole and the cavity are formed in the same step.

20. The method for fabricating a chip package structure as claimed in claim 19, wherein the upper-level hole and the lower-level hole are formed at different steps.