Method for Forming a Patterned Thick Metallization atop a Power Semiconductor Chip

• US 20100181617A1
• Filed: 01/20/2009
• Published: 07/22/2010
• Est. Priority Date: 01/20/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Inventors: Lee, Il Kwan
• Granted Patent: US 8,067,304 B2
• Time in Patent Office: Days
• US Class Current: 257/341
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48724 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48824 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

Claims

1. A method for forming a patterned thick metallization atop a surface insulation layer of a power semiconductor chip with a plurality of pre-patterned contact zones thereon, the method comprises:

a) providing a nearly completely fabricated semiconductor chip wafer together with its built-in alignment mark ready for metallization;

b) depositing a bottom metal layer, atop the wafer, of sub-thickness TK1 using a hot metal process;

c) depositing a top metal layer, atop the bottom metal layer, of sub-thickness TK2 using a cold metal process thus forming a composite thick metallization of total thickness TK=TK1+TK2; and

d) patterning, referencing the built-in alignment mark, the composite thick metallization

whereby form a patterned thick metallization with the process advantages of;

1. Better metal step coverage owing to the superior metal step coverage of the hot metal process as compared to that of the cold metal process; and

2. Lower alignment error rate owing to the lower alignment signal noise of the cold metal process as compared to that of the hot metal process.

2. The method for forming a patterned thick metallization of claim 1 further comprises selecting said sub-thickness TK1 and said sub-thickness TK2 such that the total thickness TK does not exceed a pre-determined maximum total thickness TK_max beyond which an unacceptable alignment error rate results owing to an excessive alignment signal noise of the composite thick metallization regardless of the values of TK1 and TK2.

3. The method for forming a patterned thick metallization of claim 2 further comprises selecting said sub-thickness TK1 and said sub-thickness TK2 such that their ratio R=TK2/TK1 does not exceed a pre-determined maximum ratio R_max beyond which an unacceptable metal step coverage results owing to an insufficient sub-thickness TK1.

4. The method for forming a patterned thick metallization of claim 2 further comprises selecting said sub-thickness TK1 and said sub-thickness TK2 such that their ratio R=TK2/TK1 does not fall below a pre-determined minimum ratio R_min below which an unacceptable alignment error rate results owing to an excessive sub-thickness TK1.

5. The method for forming a patterned thick metallization of claim 1 wherein depositing the bottom metal layer using a hot metal process further comprises vacuum depositing a composition of (aluminum, silicon, copper) at a temperature exceeding 400 degree C.

6. The method for forming a patterned thick metallization of claim 5 wherein the composition of (aluminum, silicon, copper) further comprises, by weight percentage, Al of about 98˜

99%, Si of about 0.5˜

1.5% and Cu of about 0.1˜

1.0%.

7. The method for forming a patterned thick metallization of claim 6 wherein the composition of (aluminum, silicon, copper) is, by weight percentage, Al of about 98.5%, Si of about 1.0% and Cu of about 0.5%.

8. The method for forming a patterned thick metallization of claim 1 wherein depositing the top metal layer using a cold metal process further comprises vacuum depositing a composition of (aluminum, copper) at a temperature of about 300±

50 degree C.

9. The method for forming a patterned thick metallization of claim 8 wherein the composition of (aluminum, copper) further comprises, by weight percentage, Al of about 99.0˜

99.9% and Cu of about 0.1˜

1.0%.

10. The method for forming a patterned thick metallization of claim 9 wherein the composition of (aluminum, copper) is, by weight percentage, Al of about 99.5% and Cu of about 0.5%.

11. The method for forming a patterned thick metallization of claim 2 wherein said TK_max is about 4.0 to 5.0 micron.

12. The method for forming a patterned thick metallization of claim 3 wherein said R_max is about 7:

1.

13. The method for forming a patterned thick metallization of claim 4 wherein said R_min is about 3:

1.

14. The method for forming a patterned thick metallization of claim 1 further comprises selecting said sub-thickness TK1 and said sub-thickness TK2 such that TK1 is approximately 1.0 microns and TK2 is approximately 3.0 microns.

15. The method for forming a patterned thick metallization of claim 1 further comprises selecting said sub-thickness TK1 and said sub-thickness TK2 such that TK1 is approximately 0.5 microns and TK2 is approximately 3.5 microns.

16. A power semiconductor chip comprising:

an active area having a plurality of trenches filed with an insulated gate material extending into an epitaxial layer overlaying a substrate layer functioning as a drain;

body regions extending between trenches;

source regions disposed in body regions next to the trenches;

a dielectric layer overlaying the semiconductor surface with contact openings thereon; and

a metal layer overlaying the dielectric layer contacting the source regions through the contact openings, whereas said metal layer comprising a thin hot metallization layer in the bottom and a thick cold metallization layer on the top.

17. The power semiconductor chip of claim 16 wherein said hot metallization layer has a thickness between 0.5-1 micron.

18. The power semiconductor chip of claim 16 wherein said metal layer has a combined thickness of 4-5 micron for Cu wire bonding.

19. The power semiconductor chip of claim 16 wherein the ratio of Type-II metallization thickness to Type-I metallization thickness ranges from about 3:

1 to about 7;

1.

20. The power semiconductor chip of claim 16 wherein said metal layer has a top surface of step profile substantially conforming to the topography of its underlying dielectric layer.

21. The power semiconductor chip of claim 16 further comprising:

a termination area having a gate contact opening opened through the dielectric layer on top of a gate runner trench for providing metal contact to insulated gate.

22. The power semiconductor chip of claim 21 further comprising:

a metal layer overlaying the dielectric layer contacting the insulated gate through the contact openings, and said metal layer further comprising a thin Type-I metallization layer at the bottom and a thick Type-II metallization layer on the top.

23. A power semiconductor device comprising:

a power semiconductor chip with a plurality of contact zones;

a dielectric layer overlaying the semiconductor surface extending over said plurality of contact zones and having a plurality of contact openings thereon;

a first metal layer having a thickness larger than 4 micron overlaying the dielectric layer contacting a plurality of source and body regions underlying the dielectric layer through the plurality of contact openings; and

Cu bond wires connecting the metal layer to a plurality of source leads on a lead frame.

24. The power semiconductor device of claim 23 further comprising:

a gate contact opened through the dielectric layer on top of a gate runner trench;

a second metal layer overlaying the dielectric layer contacting a gate runner through the contact openings; and

a Cu bond wire connecting the second metal layer to a gate lead on a lead frame.

25. The power semiconductor device of claim 23 further comprising:

a gate contact opened through the dielectric layer on top of a gate runner trench;

a second metal layer overlaying the dielectric layer contacting a gate runner through the contact openings; and

a gold bond wire connecting the second metal layer to a gate lead on a lead frame for further improving the semiconductor area usage efficiency.