Method for Forming a Patterned Thick Metallization atop a Power Semiconductor Chip
First Claim
1. A method for forming a patterned thick metallization atop a surface insulation layer of a power semiconductor chip with a plurality of pre-patterned contact zones thereon, the method comprises:
- a) providing a nearly completely fabricated semiconductor chip wafer together with its built-in alignment mark ready for metallization;
b) depositing a bottom metal layer, atop the wafer, of sub-thickness TK1 using a hot metal process;
c) depositing a top metal layer, atop the bottom metal layer, of sub-thickness TK2 using a cold metal process thus forming a composite thick metallization of total thickness TK=TK1+TK2; and
d) patterning, referencing the built-in alignment mark, the composite thick metallizationwhereby form a patterned thick metallization with the process advantages of;
1. Better metal step coverage owing to the superior metal step coverage of the hot metal process as compared to that of the cold metal process; and
2. Lower alignment error rate owing to the lower alignment signal noise of the cold metal process as compared to that of the hot metal process.
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Accused Products
Abstract
A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.
7 Citations
25 Claims
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1. A method for forming a patterned thick metallization atop a surface insulation layer of a power semiconductor chip with a plurality of pre-patterned contact zones thereon, the method comprises:
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a) providing a nearly completely fabricated semiconductor chip wafer together with its built-in alignment mark ready for metallization; b) depositing a bottom metal layer, atop the wafer, of sub-thickness TK1 using a hot metal process; c) depositing a top metal layer, atop the bottom metal layer, of sub-thickness TK2 using a cold metal process thus forming a composite thick metallization of total thickness TK=TK1+TK2; and d) patterning, referencing the built-in alignment mark, the composite thick metallization whereby form a patterned thick metallization with the process advantages of; 1. Better metal step coverage owing to the superior metal step coverage of the hot metal process as compared to that of the cold metal process; and 2. Lower alignment error rate owing to the lower alignment signal noise of the cold metal process as compared to that of the hot metal process. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A power semiconductor chip comprising:
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an active area having a plurality of trenches filed with an insulated gate material extending into an epitaxial layer overlaying a substrate layer functioning as a drain; body regions extending between trenches; source regions disposed in body regions next to the trenches; a dielectric layer overlaying the semiconductor surface with contact openings thereon; and a metal layer overlaying the dielectric layer contacting the source regions through the contact openings, whereas said metal layer comprising a thin hot metallization layer in the bottom and a thick cold metallization layer on the top. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. A power semiconductor device comprising:
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a power semiconductor chip with a plurality of contact zones; a dielectric layer overlaying the semiconductor surface extending over said plurality of contact zones and having a plurality of contact openings thereon; a first metal layer having a thickness larger than 4 micron overlaying the dielectric layer contacting a plurality of source and body regions underlying the dielectric layer through the plurality of contact openings; and Cu bond wires connecting the metal layer to a plurality of source leads on a lead frame. - View Dependent Claims (24, 25)
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Specification