NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT VERTICAL DIODE

• US 20100181657A1
• Filed: 06/10/2009
• Published: 07/22/2010
• Est. Priority Date: 12/19/2002
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Radigan, Steven J., Herner, S. Brad
• Granted Patent: US 8,018,025 B2
• Time in Patent Office: Days
• US Class Current: 257/656
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/868 PIN diodes

Abstract

A nonvolatile memory cell includes: a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode; wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. Numerous additional aspects are provided.

Claims

1. A nonvolatile memory cell comprising:

a rail-shaped first conductor formed at a first height above a substrate;

a rail-shaped second conductor formed above the first conductor; and

a vertically oriented first pillar comprising a p-i-n first diode,

wherein the first pillar is disposed between the second conductor and the first conductor;

wherein the first diode comprises an intrinsic or lightly doped region; and

wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater.

2. The nonvolatile memory cell of claim 1, wherein the first diode further comprises a top heavily doped region having a first conductivity type and a bottom heavily doped region having a second conductivity type opposite the first conductivity type, and wherein the first diode has a first height between about 500 angstroms and about 3500 angstroms.

3. The nonvolatile memory cell of claim 1, wherein the intrinsic or lightly doped region has a first thickness of about 600 angstroms or greater.

4. The nonvolatile memory cell of claim 3, wherein the first diode further comprises a top heavily doped region having a first conductivity type and a bottom heavily doped region having a second conductivity type opposite the first conductivity type, and wherein the first diode has a first height between about 800 angstroms and about 3500 angstroms.

5. The nonvolatile memory cell of claim 4, wherein the first height of the diode is between about 1000 and about 3000 angstroms.

6. The nonvolatile memory cell of claim 4, wherein the first height of the diode is between about 1300 and about 3000 angstroms.

7. The nonvolatile memory cell of claim 4, wherein the first height of the diode is between about 1600 and about 2000 angstroms.

8. The nonvolatile memory cell of claim 3, wherein the lightly doped or intrinsic region has a first thickness of at least about 800 angstroms.

9. The nonvolatile memory cell of claim 2, wherein the top heavily doped region or the bottom heavily doped region is not doped by in situ doping.

10. The nonvolatile memory cell of claim 2, wherein the top heavily doped region or the bottom heavily doped region is doped by ion implantation, plasma immersion, gas source diffusion, or solid source diffusion.

11. The nonvolatile memory array of claim 2, wherein the top heavily doped region is doped by ion implantation.

12. The nonvolatile memory cell of claim 2, wherein the top heavily doped region is doped with BF₂.

13. The nonvolatile memory array of claim 2, wherein the bottom heavily doped region is doped by ion implantation.

14. The nonvolatile memory cell of claim 2, wherein the bottom heavily doped region is doped with arsenic.

15. The nonvolatile memory cell of claim 1, further comprising a dielectric rupture antifuse.

16. The nonvolatile memory cell of claim 15, wherein the dielectric rupture antifuse is a dielectric layer formed on the first pillar.

17. The nonvolatile memory cell of claim 16, wherein the dielectric layer is an oxide, nitride, or oxynitride layer.

18. The nonvolatile memory cell of claim 17, wherein the dielectric layer is a silicon dioxide layer formed by oxidation of a portion of the first pillar.

19. The nonvolatile memory cell of claim 1, further comprising a rail-shaped third conductor formed above the second conductor.

20. The nonvolatile memory cell of claim 19, further comprising a vertically oriented second pillar above the first pillar.

21. The nonvolatile memory cell of claim 20, wherein the vertically oriented second pillar is disposed between the second conductor and the third conductor.

22. The nonvolatile memory cell of claim 21, further comprising a rail-shaped fourth conductor formed above the third conductor.

23. The nonvolatile memory cell of claim 21, wherein the vertically oriented second pillar is disposed between the third conductor and the fourth conductor.

24. The nonvolatile memory cell of claim 1, wherein no dielectric layer is disposed between the vertically oriented first pillar and the first conductor, between the vertically oriented first pillar and the second conductor, or within the vertically oriented first pillar.

25. A monolithic three dimensional memory array comprising:

i) a first memory level, the first memory level comprising;

a) a plurality of substantially parallel, substantially coplanar first conductors formed above a substrate;

b) a plurality of substantially parallel, substantially coplanar second conductors formed above the first conductors; and

c) a plurality of vertically oriented first junction diodes;

wherein each first junction diode is disposed between one of the plurality of substantially parallel, substantially coplanar first conductors and one of the plurality of substantially parallel, substantially coplanar second conductors;

wherein the first junction diodes have a first height between about 500 angstroms and about 3500 angstroms; and

ii) at least a second memory level monolithically formed on the first memory level.

26. The monolithic three dimensional memory array of claim 25, wherein the height of the first junction diodes is between about 800 angstroms and about 3500 angstroms.

27. The monolithic three dimensional memory array of claim 25, wherein the height of the first junction diodes is between about 1300 angstroms and about 3500 angstroms.

28. The monolithic three dimensional memory array of claim 25, further comprising a plurality of first dielectric rupture antifuses.

29. The monolithic three dimensional memory array of claim 28, wherein each of the first dielectric rupture antifuses is a first dielectric layer formed on one of the first junction diodes.

30. The monolithic three dimensional memory array of claim 29, wherein the first dielectric layers comprise an oxide, nitride, or oxynitride.

31. The monolithic three dimensional memory array of claim 29, wherein the first dielectric layers comprise silicon dioxide formed by oxidation of a portion of the first junction diodes.

32. The monolithic three dimensional memory array of claim 25, wherein each of the first junction diodes comprises a bottom heavily doped region of a first conductivity type, a middle intrinsic or lightly doped region, and a top heavily doped region of a second conductivity type, the second conductivity type opposite the first conductivity type.

33. The monolithic three dimensional memory array of claim 32, wherein the top heavily doped regions are not doped by in situ doping.

34. The monolithic three dimensional memory array of claim 32, wherein the top heavily doped regions are doped by ion implantation, plasma immersion, gas source diffusion, or solid source diffusion.

35. The monolithic three dimensional memory array of claim 32, wherein the top heavily doped regions are doped by ion implantation.

36. The monolithic three dimensional memory array of claim 32, wherein the top heavily doped regions are doped with BF₂ ions.

37. The monolithic three dimensional memory array of claim 32, wherein the bottom heavily doped regions are not doped by in situ doping.

38. The monolithic three dimensional memory array of claim 32, wherein the bottom heavily doped regions are doped by ion implantation, plasma immersion, gas source diffusion, or solid source diffusion.

39. The monolithic three dimensional memory array of claim 32, wherein the bottom heavily doped regions are doped by ion implantation.

40. The monolithic three dimensional memory array of claim 32, wherein the bottom heavily doped regions are doped with arsenic ions.

41. The monolithic three dimensional memory array of claim 32, wherein the middle intrinsic or lightly doped regions have a thickness of at least about 300 angstroms.

42. The monolithic three dimensional memory array of claim 32, wherein the middle intrinsic or lightly doped regions have a thickness of at least about 600 angstroms.

43. The monolithic three dimensional memory array of claim 25, wherein the second memory level comprises:

a plurality of substantially parallel, substantially coplanar third conductors formed above the second conductors; and

a plurality of vertically oriented second junction diodes formed above the first junction diodes.

44. The monolithic three dimensional memory array of claim 43, wherein each of the second diodes is disposed between one of the second conductors and one of the third conductors.

45. The monolithic three dimensional memory array of claim 43, wherein the second memory level further comprises a plurality of substantially parallel, substantially coplanar fourth conductors formed above the third conductors, and wherein each of the second diodes is disposed between one of the third conductors and one of the fourth conductors.

46. The monolithic three dimensional memory array of claim 25, wherein the substrate comprises monocrystalline silicon.

47. A method for forming a nonvolatile memory cell, the method comprising:

forming a rail-shaped first conductor above a substrate;

forming a rail-shaped second conductor above the first conductor; and

forming a substantially vertical first pillar disposed between the first conductor and the second conductor,

wherein the first pillar comprises a vertically oriented p-i-n diode, and the p-i-n diode comprises;

a) a bottom heavily doped region having a first conductivity type,

b) a middle intrinsic or lightly doped region, and

c) a top heavily doped region having a second conductivity type opposite the first conductivity type,

wherein the bottom heavily doped region is doped by implantation of arsenic ions and the top heavily doped region is doped by implantation of BF₂ ions.

48. The method of claim 47, further comprising forming a dielectric layer between the first diode and the second conductor.

49. The method of claim 48, wherein the dielectric layer comprises an oxide, nitride, or oxynitride.

50. The method of claim 48, wherein the dielectric layer is silicon dioxide.

51. The method of claim 47, wherein the nonvolatile memory cell resides in a monolithic three dimensional memory array.

52. A method for forming a monolithic three dimensional memory array, the method comprising:

forming a plurality of substantially parallel, substantially coplanar rail-shaped first conductors above a substrate;

forming a plurality of substantially parallel, substantially coplanar rail-shaped second conductors above the first conductors; and

forming a plurality of substantially vertical first pillars;

wherein each first pillar is disposed between one of the first conductors and one of the second conductors;

wherein each of the first pillars comprises a vertically oriented p-i-n diode; and

wherein each p-i-n diode comprises;

a) a bottom heavily doped region having a first conductivity type;

b) a middle intrinsic or lightly doped region; and

c) a top heavily doped region having a second conductivity type opposite the first conductivity type;

wherein the bottom heavily doped region is doped by implantation of arsenic ions and the top heavily doped region is doped by implantation of BF₂ ions.

53. The method of claim 52, further comprising forming:

forming a plurality of substantially vertical second pillars above the first pillars; and

forming a plurality of substantially parallel, substantially coplanar rail-shaped third conductors above the second conductors.

54. The method of claim 53, wherein each of the second pillars is disposed between one of the second conductors and one of the third conductors.

55. The method of claim 53, further comprising forming a plurality of substantially parallel, substantially coplanar rail-shaped fourth conductors above the third conductors, wherein each of the second pillars is disposed between one of the third conductors and one of the fourth conductors.