STACKABLE LAYER CONTAINING BALL GRID ARRAY PACKAGE

• US 20100181662A1
• Filed: 03/25/2010
• Published: 07/22/2010
• Est. Priority Date: 07/07/2007
• Status: Active Grant

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Aprolase Development Co LLC (Intellectual Ventures LLC)
• Inventors: Boyd, W. Eric, Gann, Keith
• Granted Patent: US 7,982,300 B2
• Time in Patent Office: Days
• US Class Current: 257/690
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1064 Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Claims

1. An integrated circuit package comprising:

an encapsulated integrated circuit die including a bond pad; and

an internal printed circuit structure configured to electrically connect the bond pad to a conductive pad disposed on an outer surface of the integrated circuit package, wherein the internal printed circuit structure includes;

a first access lead electrically connected to the bond pad and to the conductive pad, wherein at least a portion of the first access lead is exposed on a lateral surface of the integrated circuit package; and

a second access lead electrically isolated from the first access lead.

2. The integrated circuit package of claim 1, wherein the integrated circuit package is a ball grid array integrated circuit package.

3. The integrated circuit package of claim 1, wherein the integrated circuit die is a pretested integrated circuit die.

4. The integrated circuit package of claim 1, wherein the integrated circuit package comprises a first conductive T-connect structure electrically connected to the first access lead and configured to form an electrical connection with a second integrated circuit die.

5. The integrated circuit package of claim 4, wherein the integrated circuit package includes a second conductive T-connect structure electrically connected to the second access lead and configured to form an electrical connection with a third integrated circuit die.

6. The integrated circuit package of claim 1, further comprising a solder ball coupled to the conductive pad.

7. The integrated circuit package of claim 1, wherein the conductive pad is electrically connected to the bond pad by a wire bond.

8. The integrated circuit package of claim 1, wherein the conductive pad is electrically connected to the bond pad by a ball bond.

9. The integrated circuit package of claim 1, wherein the conductive pad is electrically connected to the bond pad by a conductive epoxy.

10. The integrated circuit package of claim 1, wherein the integrated circuit die comprises a DDR2 memory chip.

11. The integrated circuit package of claim 1, wherein the second access lead is electrically connected to a second bond pad of the encapsulated integrated circuit die and to a second conductive pad disposed on the outer surface of the integrated circuit package, and wherein at least a portion of the second access lead is exposed on the lateral surface of the integrated circuit package.

12. The integrated circuit package of claim 1, wherein the first access lead comprises a clock-enable access lead, an on-die termination access lead, or a chip-select access lead, and wherein the second access lead comprises another of a clock-enable access lead, an on-die termination access lead, or a chip-select access lead.

13. The integrated circuit package of claim 1, wherein at least one of the first or second access leads comprises an address or data access lead or a voltage supply access lead.

14. An electronic module comprising:

a first layer including;

a first encapsulated integrated circuit; and

an internal printed circuit structure configured to electrically connect the first encapsulated integrated circuit to a conductive pad disposed on an outer surface of the integrated circuit package, wherein the internal printed circuit structure comprises a first access lead electrically connected to the first encapsulated integrated circuit and the conductive pad, and wherein at least a portion of the first access lead is exposed on a lateral surface of the electronic module;

a second layer including;

a second encapsulated integrated circuit; and

a second access lead having a portion exposed on the lateral surface of the electronic module, wherein the second access lead is electrically connected to the second encapsulated integrated circuit; and

a conductive trace disposed on the lateral surface of the electronic module and configured to electrically connect the first access lead to the second access lead.

15. The electronic module of claim 14, wherein the internal printed circuit structure of the first layer includes a third access lead electrically isolated from the first access lead, and wherein the third access lead is electrically connected to the first encapsulated integrated circuit and is exposed on the lateral surface of the electronic module.

16. The electronic module of claim 15, wherein the third access lead is electrically connected to a second conductive trace that is disposed on the lateral surface of the electronic module and that is configured to electrically connect the first encapsulated integrated circuit to a third encapsulated integrated circuit of a third layer.

17. The electronic module of claim 14, further comprising a base reroute structure electrically connected to at least one of the first layer or the second layer via the conductive trace.

18. The electronic module of claim 14, wherein the conductive trace is electrically connected to the first access lead via first conductive T-connect structure and to the second access lead via a second conductive T-connect structure.

19. The electronic module of claim 14, wherein at least one of the first or second encapsulated integrated circuits comprises a memory chip.

20. The electronic module of claim 14, wherein at least one of the first or second encapsulated integrated circuits comprises a pretested integrated circuit die.

21. A method comprising:

electrically connecting a first encapsulated integrated circuit die to an internal printed circuit structure to form a first integrated circuit package, wherein a first access lead of the internal printed circuit structure is electrically connected to a conductive pad disposed on an outer surface of the first integrated circuit package and to a bond pad disposed on the first encapsulated integrated circuit die;

removing a portion of encapsulating material from a lateral surface of the first integrated circuit package to expose the first access lead; and

electrically connecting the first access lead to a second access lead formed in a second integrated circuit package.

22. The method of claim 21, wherein said electrically connecting the first access lead to a second access lead comprises:

forming a conductive trace on the lateral surface of the first integrated circuit package; and

electrically connecting the first and second access leads to the conductive trace.

23. The method of claim 22, wherein the conductive trace is electrically connected to the first and second access leads using conductive T-connect structures.

24. The method of claim 21, wherein said electrically connecting a first encapsulated integrated circuit die to an internal printed circuit structure comprises forming a third access lead that is electrically connected to a second bond pad of the first encapsulated integrated circuit die and to a second conductive pad formed on the outer surface of the first integrated circuit package.

25. The method of claim 24, further comprising removing a portion of the encapsulating material from the lateral surface of the first integrated circuit package to expose the third access lead.

26. The method of claim 25, further comprising forming a conductive trace on the lateral surface of the first integrated circuit package to electrically connect the third access lead to another access lead of another integrated circuit package.

27. The method of claim 21, wherein the first integrated circuit package is a ball grid array integrated circuit package.

28. The method of claim 21, further comprising electrically connecting the conductive pad to the bond pad using a wire bond or a ball bond.

29. The method of claim 21, further comprising forming a plurality of conductive traces within the internal printed circuit structure and electrically connecting at least one of the plurality of conductive traces to the first access lead.