FLASH MEMORY DEVICE WITH DATA OUTPUT CONTROL

• US 20100182838A1
• Filed: 03/26/2010
• Published: 07/22/2010
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: PYEON, Hong Beom, KIM, Jin-Ki
• Granted Patent: US 8,000,144 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 8/10 Decoders

Abstract

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Claims

1. A flash memory device comprising:

a flash memory array for providing read data;

a clock input pin for receiving a clock signal;

a data interface, synchronized with the clock signal, for providing the read data, the data interface having an output enable pin for receiving a signal indicating when the read data is to be provided by the data interface.

2. The flash memory device of claim 1, wherein the signal has one logic level for enabling outputting of the read data from the data interface.

3. The flash memory device of claim 2, wherein outputting of the read data by the data interface is disabled when the signal has another logic level.

4. The flash memory device of claim 1, wherein the read data is provided by the data interface during each period of the clock signal.

5. The flash memory device of claim 1, wherein one bit of the read data is provided each period of the clock signal.

6. The flash memory device of any one of claim 1, wherein the data interface receives command data corresponding to a read operation, and further includes an input enable pin for receiving another signal indicating when the command data is present on the data interface.

7. The flash memory device of claim 6, wherein the another signal has one logic level to indicate when the command data is present on the data interface.

8. The flash memory device of claim 6, wherein the command data is received by the data interface during each period of the clock signal.

9. The flash memory device of claim 6, wherein one bit of the command data is received each period of the clock signal.

10. The flash memory device of claim 6, wherein the data interface includes an input data pin for receiving the command data, and an output data pin for providing the read data.

11. The flash memory device of claim 1, wherein the data interface outputs the read data serially while the signal is at the one logic level.

12. The flash memory device of claim 1, wherein the data interface outputs the read data in single-bit-wide data streams.

13. The flash memory device of claim 6, wherein the data interface receives the command data serially.

14. The flash memory device of claim 6, wherein the data interface receives the command data in a single-bit-wide data stream.

15. The flash memory device of claim 1, wherein the data interface receives a read address, and further includes an input enable pin for receiving another signal indicating when the read address is present on the data interface.

16. The flash memory device of claim 15, wherein the another signal has one logic level to indicate when the read address is present on the data interface.

17. The flash memory device of claim 15, wherein the read address is received on the data interface during each period of the clock signal.

18. The flash memory device of claim 15, wherein one bit of the read address is received each period of the clock signal.

19. The flash memory device of claim 15, wherein the data interface includes an input data pin for receiving the read address, and an output data pin for providing the read data.

20. The flash memory device of claim 15, wherein the data interface receives the read address serially in a single-bit-wide data stream.