REDUCING FAR-END CROSSTALK IN CHIP-TO-CHIP COMMUNICATION SYSTEMS AND COMPONENTS

• US 20100183141A1
• Filed: 11/05/2009
• Published: 07/22/2010
• Est. Priority Date: 01/22/2009
• Status: Abandoned Application

• Current Assignee: Hirose Electric Company Limited
• Original Assignee: Hirose Electric USA Inc (Hirose Electric Company Limited)
• Inventors: Takada, Toshiyuki, Arai, Tatsuya, Luk, Clement Kam Lam, Huang, Ching-Chao, Buan, Jeremy, Nagata, Masakazu, Matsuo, Tsutomu
• Application Number:
  US12/613,494
• Publication Number:
  US 20100183141A1
• Time in Patent Office: Days
• US Class Current: 379/417
• CPC Class Codes: H04M 1/76 Compensating for differences in line impedance
• CPC Class Codes: H05K 1/0245 Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
• CPC Class Codes: H05K 2201/09245 Crossing layout
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]

Abstract

The present invention involves chip-to-chip communication systems for reducing Far-End Crosstalk (FEXT) through the use of novel polarity swapping to negate the cumulative effect of FEXT. Skew adjustment is used to improve the FEXT cancellation from polarity swapping. The polarity reversal location or locations among FEXT sources are optimized to achieve maximum FEXT cancellation. The novelty polarity swapping technique can be applied to a wide variety of systems that can benefit from FEXT reduction.

Claims

1. A chip-to-chip communication system reducing Far End Crosstalk (FEXT), comprising:

a transmission end;

a receiving end;

multiple differential pairs connected to the transmission end and the receiving end;

each differential pair comprising a positive signal line and a negative signal line; and

wherein at least one of the differential pairs undergoes polarity reversal at one or more locations between a plurality of FEXT sources.

2. The chip-to-chip communication system of claim 1, wherein the positive signal line and the negative signal line of each of the multiple differential pairs are disposed at relative physical locations to each other, and wherein polarity reversal is achieved by exchanging the relative physical locations of the positive signal line and the negative signal line of each differential pair undergoing the polarity reversal at the one or more locations between the plurality of FEXT sources.

3. The chip-to-chip communication system of claim 1, wherein each of the multiple differential pairs further comprise an assignment corresponding to the positive signal line and the negative signal line, the assignment being disposed at the transmission end and the receiving end, and wherein polarity reversal is achieved by routing the at least one differential pair undergoing polarity reversal from the transmission end to the receiving end such that the assignment of the positive signal line and the negative signal line at the receiving end differs from the assignment of the positive signal line and the negative signal line at the transmission end.

4. The chip-to-chip communication system of claim 1, wherein the differential pairs are at least partially disposed in at least one of a printed circuit board, an electrical connector, a chip package, or a cable.

5. The chip-to-chip communication system of claim 1, wherein every other differential pair undergoes polarity reversal.

6. The chip-to-chip communication system of claim 5, wherein the multiple differential pairs are arranged in a staggered array configuration.

7. The chip-to-chip communication system of claim 1, wherein delay of at least one differential pair is adjusted such that skew is reduced.

8. The chip-to-chip communication system of claim 1, wherein the one or more polarity reversal locations among FEXT sources comprise at least one predetermined point optimized to achieve maximum FEXT cancellation.

10. The chip-to-chip communication system of claim 8, wherein the positive signal line and the negative signal line of each of the at least one differential pairs are disposed at relative physical locations to each other, and wherein polarity reversal is achieved by exchanging the relative physical locations of the positive signal line and the negative signal line of each differential pair undergoing polarity reversal at the one or more locations between the plurality of FEXT sources.

13. The chip-to-chip communication system of claim 8, wherein delay is adjusted in one of the at least one of differential pair or in the at least one single-ended signal line such that skew is reduced.

9. A chip-to-chip communication system reducing Far End Crosstalk (FEXT), comprising:

a transmission end;

a receiving end;

at least one single ended signal line;

at least one differential pair connected to the transmission end and the receiving end;

each differential pair comprising a positive signal line and a negative signal line; and

wherein at least one differential pair undergoes polarity reversal at one or more locations between a plurality of FEXT sources.

11. The chip-to-chip communication system of claim 9, wherein each of the multiple differential pairs further comprise an assignment disposed at the transmission end and at the receiving end, the assignment corresponding to the positive signal line and the negative signal line;

and wherein polarity reversal is achieved by routing the at least one differential pair undergoing polarity reversal from the transmission end to the receiving end such that the assignment of the positive signal line and the negative signal line at the receiving end differs from the assignment of the positive signal line and the negative signal line at the transmission end.

12. The chip-to-chip communication system of claim 9, wherein the at least one differential pair or the at least one single ended signal line are at least partially disposed in at least one of a printed circuit board, an electrical connector, a chip package, or a cable.

14. The chip-to-chip communication system of claim 9, wherein the one or more polarity reversal locations among FEXT sources comprise at least one predetermined point optimized to achieve maximum FEXT cancellation.

15. A component reducing Far End Crosstalk (FEXT), comprising:

a transmission end;

a receiving end;

multiple differential pairs connected to the transmission end and the receiving end;

each differential pair comprising a positive signal line and a negative signal line; and

wherein at least one of the differential pairs undergoes polarity reversal at one or more locations between a plurality of FEXT sources.

16. The component of claim 15, wherein the component is one of a printed circuit board, an electrical connector, a chip package, or a cable.

17. The component of claim 15, wherein the positive signal line and the negative signal line of each of the multiple differential pairs are disposed at relative physical locations to each other, and wherein polarity reversal is achieved by exchanging the relative physical locations of the positive signal line and the negative signal line of each differential pair undergoing polarity reversal at the one or more locations between the plurality of FEXT sources.

18. The component of claim 15, wherein each of the multiple differential pairs further comprise an assignment disposed at the transmission end and at the receiving end, the assignment corresponding to the positive signal line and the negative signal line;

and wherein polarity reversal is achieved by routing the at least one differential pair undergoing polarity reversal from the transmission end to the receiving end such that the assignment of the positive signal line and the negative signal line at the receiving end differs from the assignment of the positive signal line and the negative signal line at the transmission end.

19. The component of claim 15, wherein every other differential pair undergoes polarity reversal.

20. The component of claim 19, wherein the multiple differential pairs are arranged in a staggered array configuration.

21. The component of claim 15, wherein delay is adjusted in at least one differential pair such that skew is reduced.

22. The component of claim 15, wherein the one or more polarity reversal locations among FEXT sources comprise at least one predetermined point optimized to achieve maximum FEXT cancellation.

23. A component reducing Far End Crosstalk (FEXT), comprising:

a transmission end;

a receiving end;

at least one single ended signal line;

at least one differential pair connected to the transmission end and the receiving end;

each differential pair comprising a positive signal line and a negative signal line; and

wherein at least one differential pair undergoes polarity reversal at one or more locations between a plurality of FEXT sources.

24. The component of claim 23, wherein the positive signal line and the negative signal line of each of the at least one differential pair are disposed at relative physical locations to each other, and wherein polarity reversal is achieved by exchanging the relative physical locations of the positive signal line and the negative signal line of each differential pair undergoing the polarity reversal at the one or more locations between the plurality of FEXT sources.

25. The component of claim 23, wherein each of the multiple differential pairs further comprise an assignment disposed at the transmission end and at the receiving end, the assignment corresponding to the positive signal line and the negative signal line;

and wherein polarity reversal is achieved by routing the at least one differential pair undergoing polarity reversal from the transmission end to the receiving end such that the assignment of the positive signal line and the negative signal line at the receiving end differs from the assignment of the positive signal line and the negative signal line at the transmission end.

26. The component of claim 23, wherein the component is one of a printed circuit board, an electrical connector, a chip package, or a cable.

27. The component of claim 23, wherein delay is adjusted in one of the at least one of differential pair or in the at least one single-ended signal line such that skew is reduced.

28. The component of claim 23, wherein the one or more polarity reversal locations among FEXT sources comprise at least one predetermined point optimized to achieve maximum FEXT cancellation.