METHOD FOR FABRICATING A 3-D INTEGRATED CIRCUIT USING A HARD MASK OF SILICON-OXYNITRIDE ON AMORPHOUS CARBON

• US 20100184259A1
• Filed: 03/30/2010
• Published: 07/22/2010
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Radigan, Steven J., Konevecki, Michael W.
• Granted Patent: US 7,994,068 B2
• Time in Patent Office: Days
• US Class Current: 438/129
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/8615 Hi-lo semiconductor devices, e.g. memory devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays

Abstract

A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (Si_xO_yN_z) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched Si_xO_yN_z layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO₂) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.

Claims

1. A method for fabricating a 3-D monolithic memory device, comprising:

patterning a first silicon-oxynitride layer in a layered structure to provide a first patterned silicon-oxynitride layer, the layered structure includes a first amorphous carbon layer below the first silicon-oxynitride layer, and a first polycrystalline layer below the first amorphous carbon layer;

patterning the first amorphous carbon layer using the first patterned silicon-oxynitride layer to provide a first patterned amorphous carbon layer; and

patterning the first polycrystalline layer using the first patterned amorphous carbon layer to provide a first plurality of pillars which are diodes in a first level of the 3-D monolithic memory device.

2. The method of claim 1, wherein:

during the patterning of the first polycrystalline layer, a conductive layer which is provided between the first polycrystalline layer and the first patterned amorphous carbon layer is also patterned using the first patterned amorphous carbon layer.

3. The method of claim 2, wherein:

the conductive layer comprise at least one of tungsten and aluminum titanium nitride.

4. The method of claim 1, further comprising:

forming a second polycrystalline layer above the first plurality of pillars, a second amorphous carbon layer above the second polycrystalline layer, and a second silicon-oxynitride layer above the second amorphous carbon layer;

patterning the second silicon-oxynitride layer to provide a second patterned silicon-oxynitride layer;

patterning the second amorphous carbon layer using the second patterned silicon-oxynitride layer to provide a second patterned amorphous carbon layer; and

patterning the second polycrystalline layer using the second patterned amorphous carbon layer to provide a second plurality of pillars which are diodes in a second level of the 3-D monolithic memory device.

5. The method of claim 4, wherein the first plurality of pillars are electrically coupled from below to a first set of conductive rails, the method further comprising:

forming a second set of conductive rails above the first plurality of pillars and below the second plurality of pillars, the first plurality of pillars are electrically coupled from above to the second set of conductive rails, and the second plurality of pillars are electrically coupled from below to the second set of conductive rails.

6. The method of claim 1, wherein:

the first silicon-oxynitride layer has a starting thickness of about 220 to 420 Angstroms; and

the first amorphous carbon layer has a starting thickness of approximately 2700 to 3300 Angstroms.

7. The method of claim 1, wherein:

the patterning of the first polycrystalline layer using the first patterned amorphous carbon layer includes patterning one or more intermediate layers using the first patterned amorphous carbon layer and patterning the first polycrystalline layer using the one or more intermediate layers.

8. A method for fabricating a 3-D monolithic memory device, comprising:

in a layered structure, transferring a common pattern to a first silicon-oxynitride layer and a first amorphous carbon layer below the first silicon-oxynitride layer, to provide, together, first patterned silicon-oxynitride and amorphous carbon layers; and

patterning a first oxide layer below the first amorphous carbon layer using the first patterned silicon-oxynitride and amorphous carbon layers together to provide a first patterned oxide layer.

9. The method of claim 8, further comprising:

forming a first set of conductive rails in the first patterned oxide layer, the first set of conductive rails are in a first level of a 3-D monolithic memory device;

forming a polycrystalline layer above the first set of conductive rails; and

patterning the polycrystalline layer to form a plurality of pillars which are electrically coupled to the first set of conductive rails, the first plurality of pillars comprise diodes in the first level of the 3-D monolithic memory device.

10. A method for fabricating a 3-D monolithic memory device, comprising:

in a layered structure, transferring a common pattern to a first silicon-oxynitride layer and a first amorphous carbon layer below the first silicon-oxynitride layer, to provide, together, first patterned silicon-oxynitride and amorphous carbon layers; and

patterning a first polycrystalline layer below the first amorphous carbon layer using the first patterned silicon-oxynitride and amorphous carbon layers together to provide a first patterned polycrystalline layer.

11. The method of claim 10, wherein:

the patterning of the first polycrystalline layer forms a first plurality of pillars which are diodes in a first level of a 3-D monolithic memory device.

12. A method for fabricating a 3-D monolithic memory device, comprising:

forming multiple levels of diodes, one level after another, in a 3-D monolithic memory device, each level comprising a plurality of pillars formed in polycrystalline, the pillars are electrically coupled from above and below to conductive rails, each level of pillars is formed by patterning an associated polycrystalline layer using an associated hard mask, the associated hard mask is patterned using a silicon-oxynitride layer.

13. The method of claim 12, wherein:

the associated hard mask comprises amorphous carbon.

14. The method of claim 12, wherein:

the associated hard mask comprises silicon dioxide.

15. The method of claim 12, wherein:

the associated hard mask comprises at least one of silicon nitride and titanium nitride.

16. The method of claim 12, wherein:

the associated hard mask comprises tungsten.

17. The method of claim 12, wherein:

the associated hard mask comprises at least one of aluminum oxide, nickel oxide and hafnium oxide.

18. A method for fabricating a 3-D monolithic memory device, comprising:

forming multiple levels of diodes, one level after another, in a 3-D monolithic memory device, each level comprising a plurality of pillars formed in polycrystalline, the pillars are electrically coupled from above and below to conductive rails, each level of conductive rails is formed by patterning an associated oxide layer using an associated hard mask, the associated hard mask is patterned using a silicon-oxynitride layer.

19. The method of claim 18, wherein:

the oxide layer comprises silicon dioxide.

20. The method of claim 18, wherein:

the associated hard mask comprises amorphous carbon.

21. The method of claim 18, wherein:

the associated hard mask comprises silicon dioxide.

22. The method of claim 18, wherein:

the associated hard mask comprises at least one of silicon nitride and titanium nitride.

23. The method of claim 18, wherein:

the associated hard mask comprises tungsten.

24. The method of claim 18, wherein:

the associated hard mask comprises at least one of aluminum oxide, nickel oxide and hafnium oxide.