MANUFACTURING METHOD OF SEMICONDUCTOR POWER DEVICES

• US 20100184264A1
• Filed: 06/16/2008
• Published: 07/22/2010
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: Chang Sik Son
• Original Assignee: Tae Pok Rhee
• Inventors: Rhee, Tae Pok
• Granted Patent: US 8,058,127 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

Disclosed is a power semiconductor device, in particular, a trench type power semiconductor device for use in power electronic devices. A method of manufacturing the same is provided. The method of manufacturing the power semiconductor device adopts a trench MOSFET to decrease the size of the device, in place of a vertical type DMOSFET, under a situation in which the cost must be lowered owing to excessive cost competition. As the manufacturing process is simplified and the characteristics are improved, the cost is reduced, resulting in mass production and the creation of profit.

Claims

1. A method of manufacturing a power semiconductor device, comprising:

growing a first type epitaxial layer (102) on a first type high-concentration silicon substrate (101) and growing an initial oxide film (103) at a thickness ranging from 5000 to 10000;

applying a photoresist (104) on the initial oxide film (103) and performing photolithography and development, thus forming a trench pattern;

etching an exposed area of the initial oxide film (103) using the trench pattern, removing the photoresist (104), forming a screen oxide film (105) for ion implantation on an exposed area of the epitaxial layer (102), and forming a second type body region (106) through ion implantation and a drive-in process;

forming a first type high-concentration source region (107) through ion implantation;

laminating a spacer oxide film and forming a spacer (111) through dry etching;

subjecting a portion of the epitaxial layer (102) corresponding to a trench gate electrode, which is exposed upon formation of the spacer, to trench etching, thus forming a trench hole (112), cleaning an inside of the trench hole (112), growing a sacrificial oxide film (not shown), removing the sacrificial oxide film through wet etching, and then growing a gate oxide film (113);

laminating polysilicon (114), which is doped to a high concentration to form the gate electrode, thus filling the trench hole (112), removing the doped polysilicon through polysilicon etch back or CMP (Chemical Mechanical Polishing) such that the initial oxide film is exposed, and forming an interlayer insulating film (115);

laminating a photoresist for forming a contact pattern through second photolithography, and forming the pattern through the photolithography;

etching the oxide film of each of the gate electrode and the source region, and forming a second type high-concentration source region; and

conducting a process of applying a metal for a high-concentration source and a gate electrode, thus forming a metal electrode (116).

2. The method according to claim 1, wherein, upon ion implantation of the first type high-concentration source region (107), an open width of the gate region is formed to be larger by at least a trench width than an open width of the source region.

3. The method according to claim 1, wherein one guard ring (110) is defined by two or more open regions, and two body regions are brought into contact with each other to constitute one guard ring (110).

4. The method according to claim 1, wherein one guard ring (110) includes one or more body regions, and first, second or more guard rings (110) are used alone or in combinations thereof.

5. The method according to claim 1, further comprising forming a second conductivity type high-concentration region through ion implantation, after forming a contact hole.