SOLID STATE MEMORY FORMATTING

• US 20100185802A1
• Filed: 01/21/2009
• Published: 07/22/2010
• Est. Priority Date: 01/21/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Asnaashari, Mehdi, Benson, William E.
• Granted Patent: US 8,392,687 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. The memory arrays are formatted by the control circuitry that is configured to write system data to the number of memory arrays, where the system data ends at a physical block boundary; and write user data to the number of memory arrays, where the user data starts at a physical block boundary.

Claims

1. A memory controller, comprising:

control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells and wherein each memory array is formatted by the control circuitry that is configured to;

write system data to the number of memory arrays, where the system data ends at a physical block boundary; and

write user data to the number of memory arrays, where the user data starts at a physical block boundary.

2. The memory controller of claim 1, wherein the number of memory arrays include a portion for system data and a portion for user data.

3. The memory controller of claim 1, wherein the control circuitry is configured to write the system data and the user data such that it is separated by a padding of memory cells that do not contain data.

4. The memory controller of claim 3, wherein the padding of memory cells is configured such that the system data ends at a physical block boundary in the number of memory arrays and the user data starts at a physical block boundary in the number of memory arrays.

5. The memory controller of claim 3, wherein an indication of one or more physical parameters of the number of memory arrays is stored in memory in the control circuitry.

6. The memory controller of claim 5, wherein the one or more physical parameters of the number of memory arrays include array size, page size, block size, and memory cell type.

7. A memory controller, comprising:

control circuitry coupled to a number of memory arrays, wherein each of the number of memory arrays has multiple physical blocks of memory cells, wherein the control circuitry is configured to;

write file allocation data to the number of memory arrays such that user data starts at a beginning of one of the multiple physical blocks.

8. The memory controller of claim 7, wherein the control circuitry is configured to write the file allocation data so that a file allocation table ends at a physical block boundary.

9. The memory controller of claim 8, wherein the control circuitry is configured to provide a padding of erased memory cells between reserved data and the file allocation table such that the file allocation table ends at a physical block boundary.

10. The memory controller of claim 9, wherein the control circuitry is configured to provide a padding of erased memory cells between a first file allocation table and a second file allocation table.

11. The memory controller of claim 7, wherein a host device is coupled to the control circuitry to cause the control circuitry be configured to write the file allocation data to the number of memory arrays such that user data starts at the beginning of one of the multiple physical blocks.

12. The memory controller of claim 7, wherein the control circuitry has memory and a processor to cause the control circuitry be configured to write the file allocation data to the number of memory arrays such that user data starts at the beginning of one of the multiple physical blocks.

13. The memory controller of claim 7, wherein the number of memory arrays is one.

14. A method for formatting a number of memory arrays in a memory system, the method comprising;

indicating physical parameters associated with the number of memory arrays;

allocating a number of memory cells in the number of memory arrays as a storing system data;

allocating a number of memory cells in the number of memory arrays as a storing user data; and

writing user data such that the user data starts at a beginning of a physical block of the number of memory cells in the number of memory arrays.

15. The method of claim 14, wherein the system data includes a partition boot record, reserved data, a first file allocation table, and a second file allocation table.

16. The method of claim 14, including providing a number of erased memory cells between reserved data and a first file allocation table such that a second file allocation table ends at a physical block boundary.

17. The method of claim 14, including indicating one or more physical parameters associated with the number of memory arrays via an inquiry command.

18. The method of claim 14, including indicating one or more physical parameters associated with the number of memory arrays by receiving the physical parameters from a memory in a memory controller.

19. The method of claim 14, including calculating a modulus for the number of memory arrays based on the indicated physical parameters.

20. A method for formatting a solid state drive in a memory system, the method comprising:

writing data to a public boot record of a particular memory array of a number of memory arrays in a solid state drive, wherein the particular memory arrays includes a number of physical blocks of memory cells;

writing first file allocation data of the particular memory array and second file allocation data of the particular memory array; and

padding a portion of the particular memory array by not writing data in a number of memory cells between those storing reserved data and the first file allocation data such that the second file allocation data ends at a physical block boundary and such that user data starts at a physical block boundary.

21. The method of claim 20, including padding a portion of the particular memory array by not writing data in a number of memory cells between the first file allocation data and the second file allocation data such that the second file allocation data ends at a physical block boundary and such that user data starts at a physical block boundary.

22. The method of claim 20, including padding a portion of the particular memory array by not writing data in a number of memory cells between the second file allocation data and the user data such that the second file allocation data ends at a physical block boundary and such that user data starts at a physical block boundary.

23. The method of claim 20, including user writing data to a beginning of a page when writing the user data.

24. The method of claim 20, including writing user data starting at a physical block boundary based, at least partially, on one or more physical parameters of the particular memory array and a modulus for writing to the particular memory array.

25. The method of claim 24, wherein the one or more physical parameters are selected from the group including memory array size, block size, page size, and cell type.

26. A solid state memory system, comprising:

a number of memory arrays, wherein each of the number of memory arrays include a number of memory cells forming a number of physical blocks, wherein each of the physical blocks is organized into a number of pages;

a memory controller, wherein the memory controller includes control circuitry coupled to the number of memory arrays;

a host device coupled to the memory controller and including a memory access device and memory, the memory access device configured to execute instructions stored on the memory to;

write user data at a beginning of a physical block when writing data to an erased physical block selected from the number of physical blocks; and

write user data at a beginning of a page when writing data to an erased page.

27. The solid state memory system of claim 26, wherein a number of physical parameters of the number of memory arrays are sent from the memory controller to the memory access device in response to an inquiry command.

28. The solid state memory system of claim 27, wherein the number of physical parameters are used by the memory access device to calculate a modulus for the number of memory arrays.

29. The solid state memory system of claim 27, wherein the physical parameters are used by the memory access device to calculate a logical block address to write system data.

30. The solid state memory system of claim 26, wherein the physical parameters are used by the memory access device to calculate a logical block address to Site user data.