EVASION OF POWER ON SELF TEST DURING AN OPERATING SYSTEM INITIATED REBOOT

• US 20100185844A1
• Filed: 03/05/2009
• Published: 07/22/2010
• Est. Priority Date: 01/21/2009
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: George, Renjith Puthenpurackal, Srinivasan, Chandramouli
• Granted Patent: US 7,984,282 B2
• Time in Patent Office: Days
• US Class Current: 713/2
• CPC Class Codes: G06F 11/1417 Boot up procedures
• CPC Class Codes: G06F 11/2284 by power-on test, e.g. power-on self test [POST]
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake

Abstract

A system and method to evade the power on self test during an operating system initiated reboot is disclosed. In one embodiment, a method for optimizing reboot process of a computer includes determining a status of a power on self test (POST) performed during a prior booting of the computer when an operating system (OS) initiated rebooting of the computer is triggered, loading information obtained during the POST of the prior booting of the computer into a basic input output system (BIOS) of the computer if the status of the POST performed during the prior booting of the computer indicates a success of the POST, and performing the rebooting of the computer using the information, wherein a subsequent POST associated with the rebooting of the computer is skipped during the rebooting of the computer.

Claims

1. A method for optimizing reboot process of a computer, comprising:

determining a status of a power on self test (POST) performed during a prior booting of the computer when an operating system (OS) initiated rebooting of the computer is triggered;

loading information obtained during the POST of the prior booting of the computer into a basic input output system (BIOS) of the computer if the status of the POST performed during the prior booting of the computer indicates a success of the POST; and

performing the rebooting of the computer using the information, wherein a subsequent POST associated with the rebooting of the computer is skipped during the rebooting of the computer.

2. The method of claim 1, wherein a status bit for the status of the POST performed during the prior booting of the computer is set to “

0.”

3. The method of claim 2, wherein the status bit is set to “

1”

if the status bit for the status of the POST performed during the prior booting of the computer indicates a failure of the POST.

4. The method of claim 2, further comprising:

continuously monitoring respective hardware devices coupled to the computer; and

resetting the status bit in response to a change in the hardware.

5. The method of claim 4, wherein the monitoring the hardware is performed using a terminate and stay resident (TSR) installed in the OS.

6. The method of claim 4, wherein the change in the hardware comprises an addition of a new hardware device, a removal of an existing hardware device, and a failure in the existing hardware device.

7. The method of claim 1, wherein the information comprises a snapshot of boot initialization data generated by the POST performed during the prior booting of the computer.

8. The method of claim 1, wherein the determining the status of the POST performed during the prior booting of the computer further comprises:

masking a reset interrupt to a processor of the computer; and

accessing the status bit.

9. The method of claim 8, wherein the processor of the computer is reset if the status bit is 1.

10. The method of claim 1, wherein the computer comprises a personal computer (PC), a desktop, a laptop, a personal digital assistant (PDA), a workstation, a server, a mainframe, a wearable computer, a supercomputer, and a minicomputer.

11. A BIOS device for optimizing reboot process of a computer, comprising:

a status analysis module for determining a status of a power on self test (POST) performed during a prior booting of the computer when an operating system (OS) initiated rebooting of the computer is triggered;

an information loading module for loading information obtained during the POST of the prior booting of the computer into a basic input output system (BIOS) of the computer if the status of the POST performed during the prior booting of the computer indicates a success of the POST; and

an abridged reboot module for performing the rebooting of the computer using the information, wherein a POST associated with the rebooting of the computer is skipped during the rebooting of the computer.

12. The device of claim 11, wherein the information is stored in a first flash memory.

13. The device of claim 11, wherein the status is stored as a bit in a second flash memory.

14. The device of claim 11, wherein the status of the POST performed during the prior booting of the computer is updated by a terminate and stay resident (TSR) installed on the OS.

15. A computer readable medium for optimizing reboot process of a computer having instructions that, when executed by a computer, cause the computer to perform a method comprising:

determining a status of a power on self test (POST) performed during a previous booting of the computer when an operating system (OS) initiated rebooting of the computer is triggered;

loading information obtained during the POST of the previous booting of the computer into a basic input output system (BIOS) of the computer of the POST; and

rebooting the computer using the information and skipping a subsequent POST associated with the rebooting of the computer.