IMAGING DEVICE

• US 20100187407A1
• Filed: 01/28/2009
• Published: 07/29/2010
• Est. Priority Date: 01/28/2009
• Status: Active Grant

• Current Assignee: HL Klemove Corporation
• Original Assignee: Gentex Corporation
• Inventors: Van Blerkom, Daniel, Yassine, Rami, Andrus, Jeremy C., Bechtel, Jon H.
• Granted Patent: US 8,378,284 B2
• Time in Patent Office: Days
• US Class Current: 250/214.R
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14654 Blooming suppression
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/583 with different integration times

Abstract

The present invention relates to improved imaging devices having high dynamic range and to monitoring and automatic control systems incorporating the improved imaging devices.

Claims

1. An imaging device, comprising:

an array of pixels arranged in columns;

a logic transistor comprising a drain connected to a row logic function select line and an integration period selection circuit associated with each column, wherein said integration period selection circuit is configured to receive a signal from an enabled pixel and initiate a selected integration period for said enabled pixel.

2. An imaging device as in claim 1 wherein the gate of said logic transistor is connected to a column logic function select line.

3. An imaging device as in claim 1 formed on a silicon substrate wherein pixel readout circuits are placed on an opposing side of said pixel array relative to integration period selection circuits.

4. An imaging device as in claim 1 wherein said transistor is a selective transfer gate operation logic function transistor and is connected to a transfer gate in said pixel.

5. An imaging device as in claim 4 wherein a selective transfer gate operation logic function transistor is located on a common substrate proximate said array of pixels.

6. An imaging device as in claim 4 wherein said pixels are based on a 4T pixel structure.

7. An imaging device as in claim 3 wherein said transistor is a selective reset logic function transistor and is connected to a reset transistor in said pixel.

8. An imaging device as in claim 7 wherein a selective reset logic function transistor is located on a common substrate proximate said array of pixels.

9. An imaging device as in claim 7 wherein said pixels are based on a 3T pixel structure.

10. An imaging device as in claim 1 wherein an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence.

11. An imaging device as in claim 1 wherein a start of an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence.

12. An imaging device, comprising:

an array of pixels, said pixels are based on a 4T pixel structure;

each of said pixels further comprising a selective transfer gate operation logic function transistor connected to a transfer gate.

13. An imaging device as in claim 12 said selective transfer gate operation logic function transistor responds to concurrence of a signal which enables said pixel and a signal to select an integration period for said pixel

14. An imaging device as in claim 12 wherein a selective transfer gate operation logic function transistor is located on a common substrate proximate each pixel within said array of pixels.

15. An imaging device as in claim 12 wherein an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence.

16. An imaging device as in claim 12 wherein a start of an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence.

17. An imaging devices as in claim 12 configured to operate greater than 25 frames/second.

18. An imaging devices as in claim 12 comprising greater than 130 dB dynamic range.

19. An imaging device, comprising:

an array of pixels, said pixels are based on a 3T pixel structure;

each of said pixels further comprising a logic transistor comprising a drain connected to a row reset line, wherein an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence.

20. An imaging device as in claim 19 said logic transistor responds to concurrence of a signal which enables said pixel and a signal to select an integration period for said pixel

21. An imaging device as in claim 19 wherein a selective reset logic function transistor is located on a common substrate proximate each pixel within said array of pixels.

22. An imaging device as in claim 20 wherein an integration period for each pixel within said array of pixels is independently determined within a corresponding image acquisition sequence.

23. An imaging device as in claim 19 wherein a start of an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence.

24. An imaging devices as in claim 19 configured to operate greater than 25 frames/second.

25. An imaging devices as in claim 19 comprising greater than 130 dB dynamic range.

26. An imaging device as in claim 19 wherein the gate is in the high state while the drain is in a low state to configured to drain dharge from the gate of a connected transistor.

27. An imaging device, comprising:

columns of pixels, each column comprising a column circuit configured to receive an input from any selected pixel from an associated column, said column circuit is further configured to automatically select an integration period for a selected pixel and to output a signal to said selected pixel to initiate a selected integration period, wherein a first transistor within each pixel is configured to receive a first signal from a row logic function select line indicating when the pixel within said column is currently selected and a second signal from an associated column circuit indicating a selected integration period for said selected pixel, wherein said transistor outputs a signal which at least in part controls initiation of the selected integration period for said selected pixel.

28. An imaging device as in claim 27 formed on a silicon substrate wherein pixel readout circuits are placed on an opposing side of said pixel array relative to integration period selection circuits.

29. An imaging device as in claim 27 wherein said first transistor is coupled to a transfer gate transistor which initiates transfer of charge from a light induced charge accumulating site within said selected pixel to a charge storage site within said selected pixel, this action being used at least in part to initiate a selectable integration period chosen for the pixel.

30. An imaging device as in claim 27 wherein said first transistor is coupled to a reset transistor which resets said selected pixel to perform tasks which include initiation of a selectable integration period for said selected pixel.

31. An imaging device as in claim 29 wherein pixel structure is based on a 4T pixel design.

32. An imaging device as in claim 30 wherein pixel structure is based on a 3T pixel design.

33. An imaging devices as in claim 27 configured to operate greater than 30 frames/second.

34. An imaging devices as in claim 27 comprising greater than 130 dB dynamic range.

35. An imaging device, comprising:

at least a substantial subset of columns of pixels, each said column of pixels in said subset comprising a column circuit configured to receive an input from a selected pixel from an associated column, said column circuit is further configured to automatically select an integration period for said selected pixel and to output a signal to said selected pixel to initiate a selected integration period.

36. An imaging device as in claim 35 wherein all columns comprise a column circuit.

37. An imaging device as in claim 35 wherein said input to said column circuit from said selected pixel is an analog input.

38. An imaging device as in claim 37 wherein said analog input is compared to an analog threshold value within said column circuit.

39. An imaging device as in claim 35, each said column circuit comprising a memory associated with said selected pixel to record an indication of said selected integration period for said selected pixel.

40. An imaging device as in claim 39 wherein settings in said memory are used at least in part, to select an integration period for said selected pixel.

41. An imaging device as in claim 38 wherein the result of said comparison is used in part to select an integration period for said selected pixel.

42. An imaging device as in claim 35 wherein said column circuit is configured to receive an input from a selected pixel in an associated column, to select an integration period for said selected pixel and to output a signal to said selected pixel to initiate said selected integration period within a single task.

43. An imaging device as in claim 35 wherein conditional selection and initiation of integration periods occurs substantially in parallel for multiple columns, each column comprising an associated column circuit.

44. An imaging device as in claim 35 wherein a first transistor within each pixel is configured to receive a first signal indicating when the pixel within said column is currently selected and a second signal from an associated column circuit indicating a selected integration period for said selected pixel, wherein said transistor outputs a signal which at least in part controls initiation of said selected integration period for said selected pixel.

45. An imaging device as in claim 44 wherein said first transistor is coupled to a transfer gate transistor which initiates transfer of charge from a light induced charge accumulating site within said selected pixel to a charge storage site within said selected pixel, this action being used at least in part to initiate a selectable integration period chosen for the pixel.

46. An imaging device as in claim 44 wherein said first transistor is coupled to a reset transistor which resets said selected pixel to perform tasks which include initiation of a selectable integration period for said selected pixel.

47. An imaging device as in claim 35 each said pixel comprising an anti-blooming control circuit.

48. An imaging device as in claim 35 wherein pixel structure is based on a 3T pixel design.

49. An imaging device as in claim 35 wherein pixel structure is based on a 4T pixel design.

50. An imaging device as in claim 35 wherein digitized pixel readout is performed using at least one circuit at least partially distinct from a column circuit associated with selected column.

51. An imaging device as in claim 50 wherein pixel values are digitized during time periods that at least partially overlap time periods during which integration periods are chosen and initiated for pixels.

52. An imaging device as in claim 35 wherein pixel values are digitized only once per image acquisition sequence.

53. An imaging device as in claim 35 wherein selected integration periods are selected from a discrete set of available integration periods.

54. An imaging device as in claim 53 wherein available integration periods end at the same time.

55. An imaging device as in claim 35 wherein a value indicative of the light received by a pixel is based on the digitized pixel value and the integration period chosen for the pixel.

56. An imaging device as in claim 55 wherein values indicative of the light received by pixels is output in a conventional order as part of a rasterized scan sequence.

57. An imaging device as in claim 54 wherein integration periods available for pixels start at different times.

58. An imaging devices as in claim 35 configured to operate greater than 25 frames/second.

59. Am imaging devices as in claim 35 comprising greater than 130 dB dynamic range.