SOI DEVICE AND METHOD FOR ITS FABRICATION
First Claim
1. A semiconductor on insulator (SOI) device, comprising:
- a semiconductor substrate including a pn junction diode formed in a first portion of the semiconductor substrate;
a buried insulator layer overlying the semiconductor substrate;
a monocrystalline semiconductor layer overlying the buried insulator layer;
an MOS capacitor comprising;
a first plate that comprises gate electrode forming material having a first conductivity type;
a second plate that comprises an impurity doped region having the first conductivity type in the monocrystalline semiconductor layer beneath the gate electrode forming material; and
a dielectric layer disposed between the first plate and the second plate;
a first voltage bus coupled to the pn junction diode and the first plate; and
a second voltage bus coupled to the second plate such that the MOS capacitor is coupled between the first voltage bus and the second voltage bus.
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Accused Products
Abstract
A silicon on insulator (SOI) device is provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.
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Citations
18 Claims
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1. A semiconductor on insulator (SOI) device, comprising:
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a semiconductor substrate including a pn junction diode formed in a first portion of the semiconductor substrate; a buried insulator layer overlying the semiconductor substrate; a monocrystalline semiconductor layer overlying the buried insulator layer; an MOS capacitor comprising;
a first plate that comprises gate electrode forming material having a first conductivity type;
a second plate that comprises an impurity doped region having the first conductivity type in the monocrystalline semiconductor layer beneath the gate electrode forming material; and
a dielectric layer disposed between the first plate and the second plate;a first voltage bus coupled to the pn junction diode and the first plate; and a second voltage bus coupled to the second plate such that the MOS capacitor is coupled between the first voltage bus and the second voltage bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor on insulator (SOI) device comprising a p-type semiconductor substrate, a buried insulator layer overlying the p-type semiconductor substrate, and a monocrystalline semiconductor layer overlying the buried insulator layer, the SOI device further comprising:
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a pn junction diode formed in a first portion of the p-type semiconductor substrate, wherein the first portion is doped with n-type impurities to form an n-type region; a contact in a second portion of the p-type semiconductor substrate that is doped with p-type impurities; a capacitor, comprising;
a first plate comprising an n-type impurity doped region in a portion of the monocrystalline semiconductor layer, an insulator layer overlying the portion of the monocrystalline semiconductor layer, and a second plate comprising a conductive electrode overlying the insulator layer;a first bus coupled to the second plate and to the n-type region of the pn junction diode; and a second bus coupled to the first plate and to the contact in the second portion of the p-type semiconductor substrate. - View Dependent Claims (13, 14, 15, 16)
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17. A semiconductor component, comprising:
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a semiconductor on insulator (SOI) substrate having a first p-type semiconductor layer having a contact area, a layer of insulator on the first p-type semiconductor layer, and a second semiconductor layer overlying the layer of insulator; an MOS transistor comprising an n-type drain region formed in the second semiconductor layer; a pn junction diode comprising an n-type impurity doped region formed in the first p-type semiconductor layer; a capacitor comprising;
a bottom capacitor plate comprising an n-type region in the second semiconductor layer, a first n-type contact region electrically in series with the n-type region, a second n-type contact region electrically in series with the n-type region, a capacitor dielectric layer overlying the n-type region in the second semiconductor layer, and a top capacitor plate overlying the capacitor dielectric layer;a first voltage bus coupled to the n-type impurity doped region and to the top capacitor plate; a first electrical discharge path coupling the top capacitor plate to the pn junction diode; a second voltage bus coupled to the contact area in the first p-type semiconductor layer, to the n-type region in the second semiconductor layer and to the n-type drain region in the second semiconductor layer; and a second electrical discharge path coupling the bottom capacitor plate to the contact area. - View Dependent Claims (18)
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Specification