SEMICONDUCTOR MEMORY DEVICE INCLUDING A CYLINDER TYPE STORAGE NODE AND A METHOD OF FABRICATING THE SAME

• US 20100187588A1
• Filed: 08/07/2009
• Published: 07/29/2010
• Est. Priority Date: 01/29/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, Won Mo, KIM, Gil-Sub, KIM, Seong Ho, YANG, Dong Kwan
• Granted Patent: US 8,058,678 B2
• Time in Patent Office: Days
• US Class Current: 257/306
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments

Abstract

Provided is a semiconductor memory device including cylinder type storage nodes and a method of fabricating the semiconductor memory device. The semiconductor memory device includes: a semiconductor substrate including switching devices; a recessed insulating layer including storage contact plugs therein, wherein the storage contact plugs are electrically connected to the switching devices and the recessed insulating layer exposes at least some portions of upper surfaces and side surfaces of the storage contact plugs. The semiconductor device further includes cylinder type storage nodes each having a lower electrode. The lower electrode contacting the at least some portions of the exposed upper surfaces and side surfaces of the storage node contact plugs.

Claims

1. A semiconductor memory device comprising:

a semiconductor substrate including switching devices;

a recessed insulating layer including storage contact plugs therein, wherein the storage contact plugs are electrically connected to the switching devices and the recessed insulating layer exposes at least some portions of upper surfaces and side surfaces of the storage contact plugs; and

cylinder type storage nodes each having a lower electrode, the lower electrode contacting the at least some portions of the exposed upper surfaces and side surfaces of the storage node contact plugs.

2. The semiconductor memory device of claim 1, wherein an inner wall of a dielectric layer deposited on the lower electrode of the cylinder type storage nodes defines a void region around the exposed side surface of the storage node contact plugs.

3. The semiconductor memory device of claim 1, wherein the storage node contact plugs and the recessed insulating layer have an etch selectivity therebetween.

4. The semiconductor memory device of claim 1, wherein the lower electrode of the cylinder type storage nodes have an unsmooth surface morphology.

12. The semiconductor device of claim 1, wherein the switching devices are one of graphene switching devices or nano switching devices.

13. The semiconductor device of claim 1, wherein the cylinder type storage nodes further include an upper electrode and a dielectric layer disposed between the lower electrode and the upper electrode, and wherein the lower electrode of the cylinder type storage electrode is electrically connected to the switching devices via the storage node contact plugs formed in the recessed insulating layer.

14. The semiconductor device of claim 13, wherein the dielectric layer is a silicon oxide layer.

15. The semiconductor device of claim 13, wherein dielectric layer includes one or more high-k layers selected from the group consisting of a silicon nitride layer, a hafnium oxide layer, a zirconium oxide layer, a tantalum oxide layer, a titanium oxide layer, a hafnium-aluminium oxide layer, a hafnium-tantalum oxide layer, a hafnium-silicon oxide layer, an aluminium oxide layer, an aluminium nitride layer, an aluminium-gallium nitride layer, and mixtures thereof.

16. The semiconductor device of claim 1, further comprising an interlayer dielectric layer formed on the cylinder type storage nodes.

5. A semiconductor memory device comprising:

a semiconductor substrate including transistors;

bit lines formed on the semiconductor substrate and electrically connected to drains of the transistors;

a first insulating layer formed between the bit lines and including storage node contact plugs therein, wherein the storage node contact plugs are electrically connected to sources of the transistors and the first insulating layer is recessed so as to expose at least some portions of upper surfaces and side surfaces of the storage node contact plugs; and

cylinder type storage nodes each having a lower electrode which contacts at least a portion of the exposed upper surfaces and side surfaces of the storage node contact plugs.

6. The semiconductor memory device of claim 5, wherein the first insulating layer includes first spacer layers which are formed on side walls of the bit lines.

7. The semiconductor memory device of claim 6, wherein the storage node contact plugs are self-aligned between the bit lines by the first spacer layers.

8. The semiconductor memory device of claim 5, wherein the bit lines include bit line conductive layers and second spacer layers formed on side walls of the bit line conductive layers, and the first spacer layers and the second spacer layers have an etch selectivity therebetween.

9. The semiconductor memory device of claim 5, wherein at least a portion of the lower electrode of each of the cylinder type storage nodes is supported by a contact with the side wall of the bit lines.

10. The semiconductor memory device of claim 5, wherein at least a portion of the lower electrode of each of the cylinder type storage nodes is supported by a contact with a side wall of a second insulating layer formed between the bit lines.

11. The semiconductor memory device of claim 5, wherein a shape of a bottom portion of the cylinder type storage nodes is determined on the basis of a miss-alignment margin in a photolithography process.

17. The semiconductor device of claim 5, further comprising a device isolation layer formed in the semiconductor substrate to define active regions, and wherein the bit lines are disposed on the device isolation layer of the semiconductor substrate.

18. The semiconductor device of claim 5, wherein the cylinder type storage nodes further include a dielectric layer and an upper electrode sequentially formed on the lower electrode.

19. The semiconductor device of claim 5, wherein the first spacer layer is formed of one of a silicon oxide layer and a silicon nitride layer.

20. The semiconductor device of claim 5, further comprising an interlayer dielectric layer formed on the cylinder type storage nodes.