DEVICES AND METHODS FOR PREVENTING CAPACITOR LEAKAGE

• US 20100187589A1
• Filed: 04/02/2010
• Published: 07/29/2010
• Est. Priority Date: 07/20/2005
• Status: Active Grant

• Current Assignee: Kuo-Chi Tu
• Original Assignee: Kuo-Chi Tu
• Inventors: TU, Kuo-Chi
• Granted Patent: US 8,487,361 B2
• Time in Patent Office: Days
• US Class Current: 257/306
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug

Abstract

Devices and methods for preventing capacitor leakage caused by sharp tip. The formation of sharp tip is avoided by a thicker bottom electrode which fully fills a micro-trench that induces formation of the sharp tip. Alternatively, formation of the sharp tip can be avoided by recessing the contact plug to substantially eliminate the micro-trench

Claims

1. A semiconductor device, comprising:

a contact plug having a top flange; and

a capacitor landing on the contact plug with an overlay shift, comprising a bottom electrode on the contact plug, a capacitor dielectric on the bottom electrode, and a top electrode on the capacitor dielectric, with the top flange of the contact plug fitting against the capacitor.

2. The semiconductor device of claim 1, wherein the contact plug is formed over a source/drain region of a MOSFET transistor.

3. The semiconductor device of claim 1, wherein the contact plug is formed in a contact opening through a first insulating layer, and the capacitor is formed in a capacitor opening through a second insulating layer overlying the first insulating layer.

4. The semiconductor device of claim 3, further comprising a stop layer between the first insulating layer and the second insulting layer, and the capacitor opening is further formed through the stop layer.

5. The semiconductor device of claim 1, wherein the capacitor is cup-shaped.

6. The semiconductor device of claim 1, wherein the top flange of the contact plug fits against the bottom sidewall of the capacitor.

7. A method of forming a semiconductor device, comprising:

forming a contact plug in a first insulating layer;

forming a second insulating layer overlying the contact plug and the first insulating layer;

forming a capacitor opening in the second insulating layer down to the contact plug with an overlay shift, the capacitor opening comprising a trench portion below the insulating layer, exposing at least part of the sidewall of the contact plug; and

recessing the contact plug; and

forming a capacitor on the recessed contact plug.

8. The method of claim 7, wherein the contact plug is formed over a source/drain region of a MOSFET transistor.

9. The method of claim 7, further comprising, before forming the second insulating layer, forming a stop layer overlying the contact plug, wherein the formation of the capacitor opening further comprises forming the capacitor opening through the stop layer.

10. The method of claim 7, wherein the contact plug is recessed to about the same depth as the trench portion.

11. The method of claim 7, wherein the contact plug is recessed below the trench portion.

12. The method of claim 7, wherein the contact plug is recessed with a remaining sidewall portion above the trench portion.