METHODS FOR MAKING SEMICONDUCTOR DEVICES USING NITRIDE CONSUMPTION LOCOS OXIDATION

• US 20100187602A1
• Filed: 01/29/2009
• Published: 07/29/2010
• Est. Priority Date: 01/29/2009
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Olsen, Tony L., Woolsey, Debra S., Madson, Gordon K.
• Application Number:
  US12/362,321
• Publication Number:
  US 20100187602A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/76202 using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO H01L21/76235 takes precedence; together with vertical isolation, e.g. LOCOS in a SOI substrate, H01L21/76264
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Semiconductor devices and methods for making such devices using nitride consumption LOCOS oxidation are described. The semiconductor devices contain a planar field oxide structure that has been grown using a nitride layer as an oxidation mask. Once the field oxide structure has been grown, the nitride mask is not etched away, but rather converted to an oxide layer by an oxidation process using radicals of hydrogen and oxygen. The semiconductor devices also contain a shielded gate trench MOSFET that can be created using an oxide layer with an overlying nitride layer as the channel (sidewall) gate dielectric. An inter-poly-dielectric (IPD) layer can be formed from a thermally grown oxide which uses the nitride layer as a oxidation mask. The thickness of the IPD layer can be adjusted to any thickness needed with minimal effect of the channel gate dielectric layer. An oxidation process using radicals of hydrogen and oxygen can be preformed to consume the nitride layer and form the gate oxide in the channel region. Since the gate channel nitride acts as a barrier to the oxidation, the IPD oxide layer can be grown to any needed thickness with minimal oxidation to the channel gate and the nitride layer can be removed without any etching processes. Other embodiments are described.

Claims

1. A method for making a trench MOSFET device, comprising:

providing a trench in a silicon substrate;

forming a first oxide layer in the trench and on the upper surface of the substrate;

depositing a nitride layer on the oxide layer;

depositing a second oxide layer on the nitride layer;

depositing a polysilicon layer to cover the second oxide layer;

etching the first and second oxide layers and the polysilicon layer to form a shield oxide and a first polysilicon gate;

converting the nitride layer to a third oxide layer; and

forming a second polysilicon gate in the trench above the third oxide layer.

2. The method of claim 1, wherein the nitride layer is converted to the third oxide layer by heating in an atmosphere containing free radicals of hydrogen and oxygen.

3. The method of claim 1, wherein the nitride layer is converted to the third oxide layer without using any etching processes to remove the nitride layer.

4. The method of claim 1, wherein the third oxide layer is formed without converting substantially any silicon in the substrate into an oxide.

5. The method of claim 1, wherein the width of the trench is not substantially increased when the nitride layer is converted to the third oxide layer.

6. The method of claim 5, wherein the width of the upper part of the trench is substantially the same as the width of the lower part of the trench.

7. The method of claim 1, wherein the second polysilicon gate contains substantially no portion intruding into the second oxide layer.

8. A method for making a semiconductor device, comprising:

providing a silicon substrate;

forming a first oxide layer on the upper surface of the substrate;

depositing a nitride mask on the oxide layer;

increasing the thickness of the first oxide layer not covered by the nitride mask; and

converting the nitride layer to a second oxide layer.

9. The method of claim 8, wherein the nitride layer is converted to the second oxide layer by heating in an atmosphere containing free radicals of hydrogen and oxygen.

10. The method of claim 8, wherein the nitride layer is converted to the second oxide layer without using any etching processes to remove the nitride layer.

11. The method of claim 8, wherein the thickness of the first oxide layer is increased by a LOCOS process.

12. A MOSFET device made by the method comprising:

providing a trench in a silicon substrate;

forming a first oxide layer in the trench and on the upper surface of the substrate;

depositing a nitride layer on the oxide layer;

depositing a second oxide layer on the nitride layer;

depositing a polysilicon layer to cover the second oxide layer;

etching the first and second oxide layers and the polysilicon layer to form a shield oxide and a first polysilicon gate;

converting the nitride layer to a third oxide layer; and

forming a second polysilicon gate in the trench above the third oxide layer.

13. The device of claim 12, wherein the nitride layer is converted to the third oxide layer by heating in an atmosphere containing free radicals of hydrogen and oxygen.

14. The device of claim 12, wherein the nitride layer is converted to the third oxide layer without using any etching processes to remove the nitride layer.

15. The device of claim 12, wherein the third oxide layer is formed without converting substantially any silicon in the substrate into an oxide.

16. The device of claim 12, wherein the width of the trench is not substantially increased when the nitride layer is converted to the third oxide layer.

17. The device of claim 16, wherein the width of the upper part of the trench is substantially the same as the width of the lower part of the trench.

18. The device of claim 12, wherein the second polysilicon gate contains substantially no portion intruding into the second oxide layer.

19. A semiconductor device made by the method, comprising:

providing a silicon substrate;

forming a first oxide layer on the upper surface of the substrate;

depositing a nitride mask on the oxide layer;

increasing the thickness of the first oxide layer not covered by the nitride mask; and

converting the nitride layer to a second oxide layer.

20. The device of claim 19, wherein the nitride layer is converted to the second oxide layer by heating in an atmosphere containing free radicals of hydrogen and oxygen.

21. The device of claim 19, wherein the nitride layer is converted to the second oxide layer without using any etching processes to remove the nitride layer.

22. The device of claim 19, wherein the thickness of the first oxide layer is increased by a LOCOS process.

23. A semiconductor device, comprising:

a silicon substrate containing a trench in an upper portion thereof;

a pad oxide layer located in a bottom portion of the trench;

a nitride layer located on the pad oxide layer;

a shield oxide layer located on the nitride layer;

a first polysilicon gate located on shield oxide layer;

an interpoly dielectric layer located over the first polysilicon gate; and

a second polysilicon gate located on the interpoly dielectric layer in an upper portion of the trench, the second polysilicon gate insulated from the substrate by a nitride layer that has been converted to an oxide layer.

24. The device of claim 23, wherein the upper portion of the trench and the lower portion of the trench have substantially the same width.

25. The device of claim 23, wherein the second polysilicon gate contains substantially no portion intruding into the shield oxide layer.