Contacts in Semiconductor Devices

• US 20100187611A1
• Filed: 01/27/2009
• Published: 07/29/2010
• Est. Priority Date: 01/27/2009
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Ostermayr, Martin, Herold, Klaus, Marokkey, Sajan, Lian, Jenny, Schiwon, Roberto
• Application Number:
  US12/360,599
• Publication Number:
  US 20100187611A1
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: G03F 1/00 Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
• CPC Class Codes: G03F 7/0035 Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 10/18 Peripheral circuit regions

Abstract

Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance.

Claims

1. A method of manufacturing a structural building block of a semiconductor device, the method comprising:

coating a first photo resist layer over a substrate;

using a first mask, patterning the first photo resist layer thereby forming first features, the first mask comprising a first plurality of lines oriented in a first direction;

after patterning the first photo resist layer, coating a second photo resist layer;

using a second mask, patterning the second photo resist layer thereby forming second features, wherein the second mask comprises a second plurality of lines oriented in a second direction orthogonal to the first direction;

after patterning the second photo resist layer, coating a third photo resist layer; and

using a third mask, patterning the third photo resist layer thereby forming third features, wherein the first, the second, and the third features comprise a pattern for forming contact holes.

2. The method of claim 1, further comprising:

freezing the first features after patterning the first photo resist layer, wherein the second photo resist layer is coated after freezing the first features; and

freezing the second features after patterning the second photo resist layer, wherein the third photo resist layer is coated after freezing the second features.

3. The method of claim 1, wherein the contact holes are formed in regions patterned by each of the first mask, the second mask, and the third mask.

4. The method of claim 1, wherein the contact holes are formed in regions exposed by each of the first mask, the second mask, and the third mask.

5. The method of claim 1, further comprising forming an insulating layer over the substrate, wherein the first photo resist layer is coated over the insulating layer.

6. The method of claim 5, further comprising etching the insulating layer using the first, the second, and the third features as a pattern.

7. The method of claim 1, wherein the first, the second, and the third photo resists are each a positive tone resist.

8. The method of claim 1, wherein the first photo resist and the second photo resist are each a negative tone resist.

9. A semiconductor device comprising:

a first plurality of contacts disposed over a first region of a substrate, the first plurality of contacts being disposed as rows and columns on a first orthogonal grid, each row of the first plurality of contacts being spaced by a first distance, and each column of the first plurality of contacts being spaced by a second distance; and

a second plurality of contacts disposed over a second region of a substrate, the second plurality of contacts being disposed as rows and columns on a second orthogonal grid, each row of the second plurality of contacts being spaced by a third distance, and each column of the second plurality of contacts being spaced by a fourth distance.

10. The device of claim 9, wherein the first region comprises a SRAM cell, and wherein the second region comprises a logic cell.

11. The device of claim 9, wherein the first region comprises analog circuitry, and wherein the second region comprises logic circuitry.

12. The device of claim 9, wherein the first distance and the third distance are different.

13. The device of claim 12, wherein the second distance and the fourth distance are different.

14. The device of claim 9, wherein the first distance is about the same as the second distance, and wherein the third distance is about the same as the fourth distance.

15. The device of claim 9, wherein the first and the second plurality of contacts couple semiconductor regions disposed over the substrate with metal lines disposed over the substrate.

16. The device of claim 9, wherein the first and the second plurality of contacts couple between metallization levels disposed over the substrate.

17. The device of claim 9, wherein a distance between adjacent contacts along each column of the first plurality of contacts is the first distance or an integer multiple of the first minimum distance.

18. The device of claim 9, wherein a distance between adjacent contacts along each row of the first plurality of contacts is the second distance or an integer multiple of the second distance.

19. The device of claim 9, wherein a distance between adjacent contacts along each column of the second plurality of contacts is the third distance or an integer multiple of the third minimum distance, wherein a distance between adjacent contacts along each row of the second plurality of contacts is the fourth distance or an integer multiple of the fourth distance.

20. The device of claim 9, wherein a length measured along the row of the first plurality of contacts follows the equation:

length=n×

length of individual contact+(n−

1) second distance, wherein n is a positive integer.

21. The device of claim 9, wherein a width measured along the column of the first plurality of contacts follows the equation:

width=n×

width of individual contact+(n−

1) first distance, wherein n is a positive integer.

22. A SRAM cell comprising:

a first access transistor and a second access transistor;

a first NMOS transistor and a second NMOS transistor; and

a first PMOS transistor and a second PMOS transistor, wherein a first source/drain contact of the first access transistor, a first source/drain contact of the second PMOS transistor, and a first source/drain contact of the second NMOS transistor are disposed on a first row, wherein a gate contact of the first access transistor and a gate contact common to the second NMOS and the second PMOS transistors is disposed on a second row, wherein a second source/drain contact of the first access transistor, a first source/drain contact of the first PMOS transistor, a second source/drain contact of the second PMOS transistor, the second source/drain contact of the second NMOS transistor is disposed on a third row, wherein a gate contact common for the first NMOS and the first PMOS transistors and a gate contact of the second access transistor are disposed in a fourth row, wherein a second source/drain contact of the first NMOS transistor, a second source/drain contact of the first PMOS transistor, and a second source/drain of the second access transistor are disposed on a fifth row.

23. The SRAM cell of claim 22, wherein the second source/drain contact of the first access transistor comprises a first source/drain contact of the first NMOS transistor, wherein the second source/drain of the second NMOS transistor comprises the first source/drain of the second access transistor.

24. The SRAM cell of claim 22, wherein the first, the second, the third, the fourth, and the fifth rows are parallel to each other.

25. The SRAM cell of claim 22, wherein the first source/drain contact of the first access transistor, the second source/drain contact of the first access transistor, and the second source/drain contact of the first NMOS transistor are disposed in a first column, wherein the gate contact common to the second NMOS and the second PMOS transistors, the first and the second source/drain contacts of the first PMOS transistor are disposed in a second column, wherein the first source/drain contact of the second PMOS transistor, the second source/drain contact of the second PMOS transistor, and the gate contact common for the first NMOS and the first PMOS transistors are disposed in a third column, wherein the first and the second source/drain contacts of the second NMOS transistor and the second source/drain contact of the second access transistor are disposed in a fourth column.

26. The SRAM cell of claim 25, wherein the first, the second, the third, and the fourth columns are parallel to each other, and wherein the first, the second, the third, and the fourth columns are each perpendicular to the first, the second, the third, the fourth, and the fifth rows.