SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

• US 20100187642A1
• Filed: 01/23/2009
• Published: 07/29/2010
• Est. Priority Date: 01/23/2009
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Grivna, Gordon M.
• Granted Patent: US 7,851,312 B2
• Time in Patent Office: Days
• US Class Current: 257/409
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A body region is formed in a semiconductor material that has a major surface. A gate trench is formed in the epitaxial layer and a gate structure is formed on the gate trench. A source region is formed adjacent the gate trench and extends from the major surface into the body region and a field plate trench is formed that extends from the major surface of the epitaxial layer through the source and through the body region. A field plate is formed in the field plate trench, wherein the field plate is electrically isolated from the sidewalls of the field plate trench. A source-field plate-body contact is made to the source region, the field plate and the body region. A gate contact is made to the gate region.

Claims

1. A method for manufacturing a semiconductor component, comprising:

providing a semiconductor material having first and second major surfaces and having a body region;

forming a first trench in the semiconductor material, the first trench having at least one sidewall;

forming a gate structure in a portion of the first trench;

forming a source region adjacent the first trench;

forming a second trench in the semiconductor material, the second trench extending through a portion of the source region and having a sidewall;

forming a first layer of dielectric material in the second trench;

forming an electrically conductive material in a portion of the second trench, the electrically conductive material over the first layer of dielectric material in the second trench;

forming a gap between the semiconductor material and the electrically conductive material in the portion of the second trench by removing a portion of the layer of dielectric material in the second trench;

forming an electrically conductive structure in the gap; and

forming a self-aligned electrical connection that contacts the source region, the semiconductor material, the electrically conductive structure in the gap, and the electrically conductive material in the portion of the second trench to electrically connect the electrically conductive material in the second trench with the source region and the body region.

10. The method of claim 1, further including enhancing a dopant concentration of a portion of the source region.

11. The method of claim 10, wherein forming the second trench includes forming the second trench through the portion of the source region having the enhanced dopant concentration.

21. The method of claim 1, wherein forming the self-aligned electrical connection that contacts the source region, the semiconductor material, the electrically conductive structure in the gap, and the electrically conductive material in the portion of the second trench includes forming the self-aligned electrical connection as an ohmic contact.

2. (canceled)

3. The method of claim 2, wherein forming the electrically conductive material in the portion of the second trench includes forming polysilicon over the first layer of dielectric material.

4. The method of claim 3, further including forming silicide over a portion of the polysilicon that is over the first layer of dielectric material.

5. The method of claim 3, further including forming the gap between the polysilicon that is over the first layer of dielectric material and the sidewall of the second trench.

6. The method of claim 5, wherein forming the gap includes removing a portion of the first layer of dielectric material that is between the polysilicon that is over the first layer of dielectric material and the sidewall of the second trench.

7. The method of claim 5, wherein forming the electrically conductive structure in the gap includes forming polysilicon in the gap.

8. The method of claim 7, wherein the polysilicon in the gap is doped with an impurity material of a first conductivity type.

9. The method of claim 8, further including laterally diffusing the impurity material from the polysilicon that is in the gap into the semiconductor material.

12. A method for manufacturing a semiconductor component, comprising:

providing a semiconductor material;

forming a first trench in the semiconductor material;

forming a gate structure in the first trench;

forming a doped region of a first conductivity type in a portion of the semiconductor material adjacent the first trench;

forming a source region in a portion of the doped region;

forming a field plate adjacent the first trench, the field plate extending into the doped region, wherein forming the field plate comprises;

forming a second trench in the semiconductor material, the second trench having sidewalls;

forming a first layer of dielectric material over the sidewalls of the second trench; and

forming polysilicon over the sidewalls of the second trench;

recessing a portion of the first layer of dielectric material to form a gap;

forming an electrically conductive material in the gap; and

forming a self-aligned electrical interconnect that contacts the source region, the semiconductor material, the electrically conductive material in the gap, and the field plate.

15. The method of claim 12, wherein forming the electrically conductive material in the gap includes forming polysilicon in the gap.

16. The method of claim 15, further including increasing a concentration of the doped region of the first conductivity type.

22. The method of claim 12, wherein forming the self-aligned electrical interconnect that contacts the source region, the semiconductor material, the electrically conductive material in the gap, and the field plate includes forming the self-aligned electrical connection as an ohmic contact.

13. (canceled)

14. (canceled)

17. (canceled)

18. A semiconductor component, comprising:

a semiconductor material having first and second major surfaces;

a gate structure extending into the semiconductor material, wherein the gate structure comprises;

a first trench extending into the semiconductor material from the first major surface, the first trench having sidewalls and a floor;

a first layer of dielectric material formed on the sidewalls and the floor of the first trench;

a first electrically conductive material formed on the first layer of dielectric material, and further including a source region adjacent the first trench and extending from the first major surface into the semiconductor material; and

wherein the field plate comprises;

a second trench extending through the source region into the semiconductor material, the second trench having sidewalls and a floor;

a second layer of dielectric material formed on portions of the sidewalls and over the floor;

a second electrically conductive material formed on a portion of the second layer of dielectric material;

a gap filled with a third electrically conductive material, wherein the filled gap is between a portion of the sidewalls of the second trench and the second electrically conductive material; and

a fourth electrically conductive material in electrical contact with the semiconductor material, the second electrically conductive material, and the third electrically conductive material, wherein the fourth electrically conductive material serves as a self-aligned contact in contact with the field plate and the source regions.

19. The semiconductor component of claim 18, further including:

a third trench extending into the semiconductor material from the first major surface, the third trench having sidewalls and a floor;

the first layer of dielectric material formed on the sidewalls and the floor of the third trench;

the first electrically conductive material formed on the first layer of dielectric material;

the source region adjacent the third trench and extending from the first major surface into the semiconductor material; and

wherein

the second trench is between the first and third trenches.

20. The semiconductor component of claim 18, wherein the second electrically conductive material and the third electrically conductive material are polysilicon.

23. A method for manufacturing a semiconductor component, comprising:

providing a semiconductor material having first and second major surfaces and having a body region;

forming a first trench in the semiconductor material, the first trench having at least one sidewall and extending from the major surface into the semiconductor material a first depth;

forming a gate structure in a portion of the first trench;

forming a source region adjacent the first trench;

forming a second trench in the semiconductor material, the second trench extending through a portion of the source region, having a sidewall, and extending from the major surface into the semiconductor material a second depth, the second depth greater than the first depth;

forming an electrically conductive material in a portion of the second trench; and

forming a self-aligned electrical connection that electrically connects the electrically conductive material in the second trench with the source region and the body region.

24. The method of claim 23, further including:

forming a first layer of dielectric material in the second trench;

forming the electrically conductive material in the portion of the second trench over the layer of dielectric material;

forming a gap between the electrically conductive material in the portion of the second trench and the sidewall of the second trench by removing a portion of the first layer of dielectric material that is between the electrically conductive material that is over the first layer of dielectric material and the sidewall of the second trench; and

forming polysilicon in the gap.