On-Chip Heat Spreader

• US 20100187670A1
• Filed: 11/12/2009
• Published: 07/29/2010
• Est. Priority Date: 01/26/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chuan-Yi, Chou, Chen Cheng, Hao, Ching-Chen, Lin, Sheng-Yuan
• Granted Patent: US 8,314,483 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/4814 Conductive parts
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05616 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/06131 : being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/06519 : including bonding areas providing primarily thermal dissipation
• CPC Class Codes: H01L 2224/08145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16146 : the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/055 : the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/34 : Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/3677 : Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/42 : Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Claims

1. A semiconductor die comprising:

a semiconductor substrate;

at least one transistor formed in the semiconductor substrate;

an interconnect metal feature in an inter-metal dielectric (IMD) layer on a front-side surface of the semiconductor substrate the interconnect metal feature being coupled to the at least one transistor;

a dielectric layer on the IMD layer;

a bonding pad formed in the dielectric layer electrically coupled to the at least one transistor through the interconnect metal feature; and

a heat spreader formed in the first dielectric layer, the heat spreader being insulated from the bonding pad and including an elongate structure having at least one major axis extending from a center region of the front-side surface of the semiconductor substrate toward an outer edge of the front-side surface of the semiconductor substrate.

2. The semiconductor die of claim 1, further comprising:

a through substrate via (TSV) extending through the substrate;

a second dielectric layer on a back-side surface of the substrate;

a second bonding pad on the second dielectric layer, wherein the second bonding pad is coupled to the TSV; and

a second heat spreader in the second dielectric layer, the second heat spreader being insulated from the TSV and the second bonding pad.

3. The semiconductor die of claim 1, wherein the first and the second heat spreaders extend to an edge of the semiconductor die, respectively.

4. The semiconductor die of claim 1, wherein the TSV is coupled to the at least one transistor.

5. The semiconductor die of claim 1, wherein the first heat spreader comprises a material selected from the group consisting essentially of aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), gold (Au), silver (Ag), a copper-tin alloy, a gold-tin alloy, an indium-gold alloy, a lead-tin alloy, and combinations thereof.

6. A stacked chip structure comprising;

a first semiconductor die, the first semiconductor die comprising a first bonding pad on a first dielectric layer on a front-side surface, a through-silicon via (TSV) extending through the first semiconductor die, the TSV being coupled to the first bonding pad, and a first heat spreader on the first dielectric layer, the first heat spreader being insulated from the TSV and the first bonding pad and having at least one major axis extending along the front-side surface; and

a second semiconductor die attached to the first semiconductor die, the second semiconductor die comprising a second bonding pad on a second dielectric layer on a front-side surface of the second semiconductor die, wherein the second bonding pad is electrically connected to the first bonding pad.

7. The stacked chip structure of claim 6, wherein the second semiconductor die comprises a second heat spreader on the second dielectric layer, the second heat spreader being insulated from the second bonding pad and the first bonding pad.

8. The stacked chip structure of claim 6, wherein the first and the second heat spreaders respectively extend to an edge of the stacked chip structure.

9. The stacked chip structure of claim 6, wherein the first semiconductor die comprises one or more semiconductor devices, and wherein the TSV is coupled to at least one of the one or more semiconductor devices.

10. The stacked chip structure of claim 7, wherein at least one of the first heat spreader and the second heat spreader comprises a material selected from the group consisting essentially of aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), gold (Au), silver (Ag), a copper-tin alloy, a gold-tin alloy, an indium-gold alloy, a lead-tin alloy, and combinations thereof.

11. The stacked chip structure of claim 6, wherein the first semiconductor die comprises a third bonding pad on a third dielectric layer on a back-side surface, the third bonding pad being coupled to the TSV.

12. The stacked chip structure of claim 11 further comprising a third heat spreader on the third dielectric layer, the third heat spreader being insulated from the third bonding pad and the TSV.

13. An electronic package comprising:

a packaging substrate;

a first semiconductor die on the packaging substrate, the first semiconductor die comprising a first bonding pad on a first dielectric layer on a front-side surface of the first semiconductor die, a bonding pad on a second dielectric layer on a back-side surface of the first semiconductor die, a through-silicon via (TSV) coupled to the one first and the second bonding pads, respectively, and a first heat spreader on the first dielectric layer, the first heat spreader being insulated from the first bonding pads and the TSV;

a second semiconductor die on the first semiconductor die, the second semiconductor die having a bonding pad on a third dielectric layer on a front-side surface of the second semiconductor die, wherein the second semiconductor die is electrically coupled to the first semiconductor die via the third bonding pad and the first bonding pad; and

a package housing filled with a thermal conducting medium, the thermal conducting medium contacting the first heat spreader.

14. The electronic package of claim 13, further comprising a second heat spreader in the second dielectric layer of the first semiconductor die, the second heat spreader being insulated from the second bonding pad and the TSV and contacting the thermal conducting medium.

15. The electronic package of claim 13, further comprising a third heat spreader in the third dielectric layer of the second semiconductor die, the third heat spreader being insulated from the bonding pad and the second bonding pad and contacting the thermal conducting medium.

16. The electronic package of claim 13, wherein the first semiconductor die comprises a semiconductor device, and wherein at the TSV is electrically coupled to semiconductor device.

17. The electronic package of claim 13, wherein the first semiconductor die is coupled to the packaging substrate at the bonding pad and through a solder ball.

18. The electronic package of claim 15, wherein at least one of the first heat spreader, the second heat spreader, and the third heat spreader includes an elongate structure having a major axis extending from a center region of the die to an outer edge of the die.

19. The electronic package of claim 13, wherein the second semiconductor die comprises a second TSV, the second TSV being coupled to the third bonding pad.

20. The electronic package of claim 13, further comprising a heat sink attached to the package housing.