Forming Seal Ring in an Integrated Circuit Die

• US 20100187671A1
• Filed: 11/13/2009
• Published: 07/29/2010
• Est. Priority Date: 01/26/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Sheng-Yuan, Lin, Chuan-Yi, Chou, Chen Cheng, Hao, Ching-Chen
• Granted Patent: US 8,168,529 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05616 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/585 : comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.

Claims

1. A device comprising:

a first die having a substrate, the substrate having formed thereon an active circuit region having one or more semiconductor devices;

a plurality of metal interconnect layers formed over the substrate, including a top metal interconnect layer;

a through-silicon via (TSV) extending from the top metal interconnect layer through the substrate;

a seal ring interposed between the active region and the TSV, the seal ring comprising a plurality of stacked features formed in respective ones of the plurality of metal interconnect layers.

2. The device of claim 1 further comprising at least one additional metal layer above the top metal interconnect layer.

3. The device of claim 1 wherein the seal ring is substantially aligned with a periphery of the active circuit region.

4. The device of claim 1 further comprising:

a dielectric layer over the top metal layer; and

a bonding contact on the dielectric layer, wherein the bonding contact is coupled to the TSV and to at least one of the semiconductor devices through a redistribution feature in a first insulating layer between the dielectric layer and the top metal interconnect layer.

5. The device of claim 4 further comprising:

a second die, the first die being coupled to the second die through the bonding contact on the first substrate and a corresponding bonding contact on the second die.

6. The device of claim 5 further comprising:

a second dielectric layer over a back-side surface of the first die; and

a second bonding contact on the second dielectric layer, wherein the second bonding contact is coupled the TSV through a second redistribution features in a second insulating layer between the second dielectric layer and the back-side surface of the first die.

7. A method of forming a semiconductor device, the method comprising:

forming one or more semiconductor devices in an active circuit region of a first semiconductor die;

forming one or more inter-metal dielectric (IMD) layers over a front-side surface of the first semiconductor die;

forming interconnect metal features in the active circuit region, the interconnect metal features being coupled to the one or more semiconductor devices and being formed in respective ones of the one or more IMD layers;

forming a seal ring in the one or more IMD layers, the seal ring enclosing the interconnect metal features in the active circuit region;

forming a recess in the one or more IMD layers and in the first semiconductor die, after the formation of the seal ring, the recess being separated from the active circuit region by the seal ring; and

filling the recess with conductive material, thereby forming a through-silicon via (TSV).

8. The method of claim 7, wherein the seal ring comprises a plurality of stacked metal rings in a plurality of interconnect metal layers in the one or more IMD layers, the respective stacked metal rings being connected together through one or more via.

9. The method of claim 7, wherein the seal ring has a shape selected from a group consisting of a square, a rectangle, a polygon, a continuous curve, and a discontinuous curve, and wherein the seal ring is substantially aligned with a periphery of the active circuit region.

10. The method of claim 7, wherein the seal ring is a continuous metallic feature surrounding the active circuit region.

11. The method of claim 7, wherein the forming the plurality of interconnect metal features in the active circuit region and the forming the seal ring are performed through a common processing flow.

12. The method of claim 7, wherein the one or more conductive materials is selected from the group consisting essentially of copper, tungsten, aluminum, cobalt, gold, silver, platinum, silicon and combinations thereof.

13. The method of claim 7 further comprising:

forming a first insulating layer over the one or more IMD layers;

forming a first dielectric layer on the first insulating layer; and

forming a first bonding contact on the first dielectric layer, wherein the first bonding contact is coupled to the TSV and to at least one of the plurality of interconnect metal features through a redistribution features in the first insulating layer.

14. The method of claim 13 further comprising:

forming a second insulating layer on a back-side surface of the semiconductor die;

forming a second dielectric layer on the second insulating layer; and

forming a second bonding contact on the second dielectric layer, wherein the second bonding contact is coupled to a second TSVs through a second redistribution feature in the second insulating layer.

15. The method of claim 13 further comprising:

bonding the first semiconductor die to a second semiconductor die through the first bonding contact on the first semiconductor die and a corresponding bonding contact on the second semiconductor die.

16. A method of forming through-silicon-vias (TSV) in a semiconductor device, the method comprising:

providing a semiconductor substrate;

forming one or more inter-metal dielectric (IMD) layers on the semiconductor substrate;

forming one or more semiconductor devices in an active circuit region of the semiconductor substrate;

forming a plurality of interconnect metal features in the IMD layers in the active circuit region;

forming a seal ring in the IMD layers, the seal ring enclosing the plurality of interconnect metal features in the active circuit region;

forming one or more recesses in a TSV region of the IMD layers and the semiconductor substrate, the TSV region being separated from active circuit region by the seal ring; and

filling the one or more recesses with one or more conductive materials, thereby forming one or more TSVs.

17. The method of claim 16, wherein the seal ring comprises a plurality of stacked metal rings in the one or more IMD layers, the stacked metal rings being connected together through one or more via rings in the one or more IMD layers.

18. The method of claim 16, wherein the forming the active circuit region and the forming the seal ring are performed through a common processing flow, prior to the forming the one or more recesses in the one or more IMD layers in the TSV region.

19. The method of claim 16, wherein forming a seal ring comprises forming a plurality of stacked ring features in respective ones of the IMD layers and interconnecting the stacked ring features with a plurality of stacked via structures.

20. The method of claim 16, wherein the forming the one or more recesses is performed at least in part by a first etching process removing the one or more IMD layers, followed by a second etch process etching the semiconductor substrate.