Through-Silicon Via Sidewall Isolation Structure

• US 20100187694A1
• Filed: 11/12/2009
• Published: 07/29/2010
• Est. Priority Date: 01/28/2009
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chiou, Wen-Chih, Wu, Weng-Jin
• Application Number:
  US12/617,494
• Publication Number:
  US 20100187694A1
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/30105 Capacitance

Abstract

A system and method for an improved through-silicon via isolation structure is provided. An embodiment comprises a semiconductor device having a substrate with electrical circuitry formed thereon. One or more dielectric layers are formed over the substrate, and an opening is etched into the structure extending from a surface of the one or more dielectric layers through the one or more dielectric layers into the substrate; the opening having sidewalls. A low-K dielectric layer is formed over the sidewalls of the opening. The opening is filled with a conductive material and/or a barrier layer creating a through-silicon via that is isolated from the surrounding substrate by the low-K dielectric layer.

Claims

1. A semiconductor device comprising:

a substrate having electrical circuitry formed thereon;

one or more dielectric layers formed over the substrate;

an opening extending through the one or more dielectric layers into the substrate, the opening filled with a conductive material; and

a low-K dielectric layer interposed between the substrate and the conductive material.

2. The semiconductor device of claim 1, further comprising a barrier layer interposed between the low-K dielectric layer and the conductive material.

3. The semiconductor device of claim 1, wherein the low-K dielectric layer comprises a material having a dielectric constant of less than about 4.

4. The semiconductor device of claim 1, wherein the low-K dielectric layer comprises a material selected from the group consisting of Si—

O—

H, Si—

O—

C—

H, and combinations thereof

5. The semiconductor device of claim 1, wherein the conductive layer comprises a material selected from the group consisting of copper, copper alloys, aluminum, tungsten, silver, polysilicon, and combinations thereof.

6. A method for creating a semiconductor device, the method comprising:

providing a substrate having a circuit side and a backside opposite the circuit side;

forming an opening in the substrate extending from the circuit side into the substrate, the opening having sidewalls;

forming a low-K dielectric layer along the sidewalls of the opening;

forming a conductive layer in the opening; and

exposing the conductive layer on the backside of the substrate.

7. The method of claim 6, wherein the method further comprises forming a barrier layer over the low-K dielectric layer prior to forming the conductive layer.

8. The method of claim 6, wherein the forming the low-K dielectric layer comprises a spin-on coating process.

9. The method of claim 6, wherein the low-K dielectric layer comprises a dielectric material having a dielectric constant of less than about 4.

10. The method of claim 6, wherein the low-K dielectric layer comprises a dielectric material selected from the group of materials consisting essentially of Si—

O—

H, Si—

O—

C—

H, or combinations thereof.

11. The method of claim 6, further comprising the opening extending through one or more dielectric layers formed on the circuit side of the substrate.

12. The method of claim 6, wherein the forming the conductive layer comprises an electroplating process.

13. The method of claim 6, wherein the conductive layer comprises a material selected from the group consisting of copper, copper alloys, aluminum, tungsten, silver, polysilicon, and combinations thereof.

14. A method for creating a semiconductor device, the method comprising:

providing a substrate having a circuit side and a backside opposite the circuit side;

forming circuitry on the circuit side of the substrate;

forming one or more dielectric layers over the circuit side of the substrate;

forming an opening in the substrate extending from a surface of the one or more dielectric layers, the opening having sidewalls;

forming a low-K dielectric layer over the sidewalls of the opening; and

forming a conductive layer over the low-K dielectric layer such that the opening is filled with the conductive layer.

15. The method of claim 14, wherein the method further comprises forming a barrier layer over the low-K dielectric layer prior to forming the conductive layer.

16. The method of claim 14, wherein the forming the low-K dielectric layer comprises a spin-on coating process.

17. The method of claim 14, wherein the low-K dielectric layer comprises a material having a dielectric constant of less than about 4.

18. The method of claim 14, wherein the low-K dielectric layer comprises a material selected from the group consisting of Si—

O—

H, Si—

O—

C—

H, or combinations thereof.

19. The method of claim 14, further comprising exposing the conductive layer on the backside of the substrate.

20. The method of claim 14, wherein the forming the conductive layer comprises an electroplating process.