Semiconductor integrated circuit, method for driving semiconductor integrated circuit, method for driving electronic apparatus, display device, and electronic apparatus

• US 20100188144A1
• Filed: 12/08/2009
• Published: 07/29/2010
• Est. Priority Date: 12/10/2008
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Iriguchi, Chiharu
• Granted Patent: US 8,610,470 B2
• Time in Patent Office: Days
• US Class Current: 327/566
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration

Abstract

The present invention provides a semiconductor integrated circuit capable of achieving high voltage. The proposed semiconductor integrated circuit includes a first node [VOUT] connected to a first potential node [VDD], and a first n-channel transistor [NT1] and a second n-channel transistor [NT2] serially connected between a first node [VOUT] and a second potential node [VSS] of a lower potential than the first potential node. One end of NT1 is connected to the second potential node [VSS], the other end thereof is connected to one end of the second n-channel transistor [NT2], a gate terminal thereof is connected to a second node [VIN], the other end of NT2 is connected to the first node [VOUT], and a gate terminal thereof is connected to a first intermediate range potential [VM1] positioned between the first potential node [VDD] and the second potential node [VSS].

Claims

1. A semiconductor integrated circuit, comprising:

a first node coupled to a first potential node;

a first n-channel transistor having one end and another end, the one end of the first n-channel transistor being coupled to a second potential node having a lower potential than the first potential node, a gate terminal of the first n-channel transistor being coupled to a second node; and

a second n-channel transistor having one end and another end, the one end of the second n-channel transistor being coupled to the first node, a gate terminal of the second n-channel transistor being applied with a first intermediate range potential having a potential between the first potential node and the second potential node, the second n-channel transistor being serially coupled to the first n-channel transistor.

2. The semiconductor integrated circuit according to claim 1, further comprising:

a third n-channel transistor having one end and another end, the one end of the third n-channel transistor being coupled to the first node and the another end of the third n- channel transistor being coupled to the another end of the second n-channel transistor, a gate terminal of the third n-channel transistor being applied with a second intermediate range potential having a higher potential than the first intermediate range potential, the second intermediate range potential having a potential between the first potential node and the second potential node.

5. The semiconductor integrated circuit according to claim 1, further comprising:

a first p-channel transistor having one end and another end, the one end of the first p-channel transistor being coupled to the first potential node, a gate terminal of the first p-channel transistor being coupled to the second node; and

a second p-channel transistor having one end and another end, the second p-channel transistor being serially coupled to the first p-channel transistor, the one end of the second p-channel transistor being coupled to the first node, a gate terminal of the second p-channel transistor being applied with a third intermediate range potential having a potential between the first potential node and the second potential node.

6. The semiconductor integrated circuit according to claim 5, further comprising:

a third p-channel transistor coupled between the first node and the one end of the second p-channel transistor, a gate terminal of the third p-channel transistor being applied with a fourth intermediate range potential having a lower potential than the third intermediate range potential, the fourth intermediate range potential having a potential between the first potential node and the second potential node.

19. A display device comprising the semiconductor integrated circuit according to claim 1.

20. An electronic apparatus comprising the display device according to claim 19.

3. A semiconductor integrated circuit, comprising:

a first node coupled to a second potential node;

a first p-channel transistor having one end and another end, the one end of the first p-channel transistor being coupled to a first potential node, the first potential node having a higher potential than the second potential node; and

a second p-channel transistor having one end and another end, the second p-channel transistor being serially coupled to the first p-channel transistor, the one end of the second p-channel transistor being coupled to the first node, a gate terminal of the second p-channel transistor being applied with a first intermediate range potential having a potential between the first potential and the second potential.

4. The semiconductor integrated circuit according to claim 3, further comprising:

a third p-channel transistor coupled between the first node and the one end of the second p-channel transistor, a gate terminal of the third p-channel transistor being applied with a second intermediate range potential having a lower potential than the first intermediate range potential, the second intermediate range potential having a potential between the first potential node and the second potential node.

7. A method for driving a semiconductor integrated circuit, the semiconductor integrated circuit including a first node coupled to a first potential node, a first n-channel transistor having one end and another end, the one end of the first n-channel transistor being applied with a second potential node having a lower potential than the first potential node, and a second n-channel transistor having one end and another end, the second n-channel transistor being serially coupled to the first n-channel transistor, the one end of the second n-channel transistor being coupled to the first node, the method comprising:

applying a first intermediate range potential having a potential between the first potential node and the second potential node to a gate terminal of the second no-channel transistor upon outputting a signal of a high potential level from the first node when a signal input to a gate terminal of the first n-channel transistor has a low potential level.

8. The method for driving a semiconductor integrated circuit according to claim 7, the semiconductor integrated circuit further including a third n-channel transistor coupled between the first node and the one end of the second n-channel transistor, the method further comprises:

applying a second immediate range potential having a potential between the first potential node and the second potential node to a gate terminal of the third n-channel transistor upon outputting of a signal of a high potential level.

18. A method for driving an electronic apparatus, comprising:

driving a semiconductor integrated circuit according to claim 7.

9. A method for driving a semiconductor integrated circuit, the semiconductor integrated circuit including a first node coupled to a second potential node, a first p-channel transistor having one end and another end, the one end of the first p-channel transistor being coupled to a first potential node, the first potential node having a higher potential than the second potential node, and a second p-channel transistor having one end and another end, the second p-channel transistor being serially coupled to the first p-channel transistor, the one end of the second p-channel transistor being coupled to the first node, the method comprises:

applying a first intermediate range potential having a potential between the first potential and the second potential to a gate terminal of the second p-channel transistor upon outputting a signal of a low potential level from the first node when a signal input to a gate terminal to the first p-channel transistor has a high potential level.

10. The method for driving a semiconductor integrated circuit according to claim 9, the semiconductor integrated circuit further including a third p-channel transistor coupled between the first node and the one end of the second p-channel transistor, the method further comprises:

applying a second intermediate range potential that is a lower potential than the first intermediate range potential to a gate terminal of the third p-channel transistor upon outputting the signal of a low potential level, the first intermediate range potential having a potential between the first potential node and the second potential node.

11. A semiconductor integrated circuit, comprising:

a first node coupled to a first potential node;

a first n-channel transistor having one end and another end, the one end of the first n-channel transistor being coupled to a second potential node, and a gate terminal of the first n-channel transistor being coupled to a second node;

a second n-channel transistor having one end and another end, the another end of the first n-channel transistor being coupled to the one end of the second n-channel transistor, a gate terminal of the second n-channel transistor being applied with a first intermediate range potential node with a potential between the first potential node and the second potential node; and

a third n-channel transistor having one end and another end, the another end of the second n-channel transistor being coupled to the one end of the third n-channel transistor and a gate terminal of the third n-channel transistor being applied with the first potential node, the first n-channel transistor, the second n-channel transistor and the third n-channel transistor being serially coupled between the first node and the second potential node of a lower potential than the first potential node.

13. The semiconductor integrated circuit according to claim 11, further comprising:

a first p-channel transistor having one end and another end, the one end of the first p-channel transistor being coupled to the first potential node;

a second p-channel transistor having one end and another end, the another end of the first p-channel transistor being coupled to the one end of the second p-channel transistor, and a gate terminal of the first p-channel transistor being coupled to a third node;

a third p-channel transistor having one end and another end, the another end of the second p-channel transistor being coupled to the one end of the third p-channel transistor, and a gate terminal of the second p-channel transistor being applied with the first intermediate range potential node with a potential between the first potential node and the second potential node, the one end of the third p-channel transistor being coupled to the first node and a gate terminal of the third p-channel transistor being applied with the second potential node;

a fourth p-channel transistor having one end and another end, the one end of the fourth p-channel transistor being coupled to the first potential node, and a gate terminal of the fourth p-channel transistor being coupled to the first node;

a fifth p-channel transistor having one end and another end, the another end of the fourth p-channel transistor being coupled to the one end of the fifth p-channel transistor, a gate terminal of the fifth p-channel transistor being applied with the first intermediate range potential node; and

a sixth p-channel transistor having one end and another end, the another end of the fifth p-channel transistor being coupled to the one end of the sixth p-channel transistor, the another end of the sixth p-channel transistor being coupled to the third node, and a gate terminal of the six p-channel transistor being applied with the second potential node, the fourth p-channel transistor, the fifth p-channel transitor and the six p-channel transistor being serially coupled between the third node and the first potential node.

14. The semiconductor integrated circuit according to claim 13, the first p-channel transistor, the second p-channel transistor, the third p-channel transistor, the first n-channel transistor, the second n-channel transistor, and the third n-channel transistor being thin film transistors.

15. The semiconductor integrated circuit according to claim 13, a semiconductor layer of the first p-channel transistor, the second p-channel transistor, the third p-channel transistor, the first n-channel transistor, the second n-channel transistor, and the third n-channel transistor being formed from polysilicon.

12. A semiconductor integrated circuit, comprising:

a first node coupled to a second potential node;

a first p-channel transistor having one end and another end, the one end of the first p-channel transistor being coupled to a first potential node, and a gate terminal of the first p-channel transistor being coupled to a second node;

a second p-channel transistor having one end and another end, the another end of the first p-channel transistor being coupled to the one end of the second p-channel transistor, a gate terminal of the second p-channel transistor being applied with a first intermediate range potential node with a potential between the first potential node and the second potential node; and

a third p-channel transistor having one end and another end, the another end of the second p-channel transistor being coupled to the one end of the third p-channel transistor, the another end of the third p-channel transistor being coupled to the first node, and a gate terminal of the third p-channel transistor being applied with the second potential node, the first p-channel transistor, the second p-channel transistor and the third p-channel transistor being serially coupled between the first node and the first potential node of a higher potential than the second potential node.

16. A method for driving a semiconductor integrated circuit, the semiconductor integrated circuit including a first node coupled to a first potential node, a first n-channel transistor having one end and another end, the one end of the first n-channel transistor being coupled to a second potential node, a second n-channel transistor having one end and another end, the another end of the first n-channel transistor being coupled to the one end of the second n-channel transistor, and a third n-channel transistor having one end and another end, the another end of the second n-channel transistor being coupled to the one end of the third n-channel transistor, and the another end of the third n-channel transistor being coupled to the first node, the first n-channel transistor, the second n-channel transistor, and the third n-channel transistor being serially coupled between the first node and the second potential node of a lower potential than the first potential node, the method comprising:

applying a potential of the first potential node to a gate terminal of the third n-channel transistor and additionally applying a first intermediate range potential with a potential between the first potential node and the second potential node to a gate terminal of the second n-channel transistor upon inputting a signal to a gate terminal of the first n-channel transistor and outputting a signal from the first node.

17. A method for driving a semiconductor integrated circuit, the semiconductor integrated circuit including a first node coupled to a second potential node, a first p-channel transistor having one end and another end, the one end of the first p-channel transistor being coupled to a first potential node, a second p-channel transistor having one end and another end, the another end of the first p-channel transistor being coupled to the one end of the second p-channel transistor, and a third p-channel transistor having one end and another end, the another end of the second p-channel transistor being coupled to the one end of the third p-channel transistor, the other end of the third p-channel transistor being coupled to a first node, the first p-channel transistor, the second p-channel transistor, and the third p-channel transistor being serially coupled between the first node and a the first potential node of a higher potential than the second potential node, the method comprising:

applying a potential of the second potential node to a gate terminal of the third p-channel transistor and additionally applying a first intermediate range potential with a potential between the first potential node and the second potential node to a gate terminal of the second p-channel transistor upon inputting a signal to a gate terminal of the first p-channel transistor and outputting a signal from the first node.