IMAGING DEVICE

• US 20100188540A1
• Filed: 01/28/2009
• Published: 07/29/2010
• Est. Priority Date: 01/28/2009
• Status: Active Grant

• Current Assignee: HL Klemove Corporation
• Original Assignee: Gentex Corporation
• Inventors: Andrus, Jeremy C., Bechtel, Jon H., Blerkom, Daniel Van
• Granted Patent: US 8,144,223 B2
• Time in Patent Office: Days
• US Class Current: 348/302
• CPC Class Codes: H04N 25/57 Control of the dynamic range
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

The present invention relates to improved imaging devices having high dynamic range and to monitoring and automatic control systems incorporating the improved imaging devices.

Claims

1. An imaging device, comprising:

an array of pixels and at least one charge overflow detection circuit configured to dynamically determine an integration period for at least one pixel.

2. An imaging device as in claim 1 further comprising compensation for charge loss.

3. An imaging device as in claim 1 further comprising correlated double sampling for final readout of a pixel value.

4. An imaging device as in claim 1 further comprising correlated double sampling for the charge overflow detection reading.

5. An imaging device as in claim 1 further comprising a 4 transistor based pixel design comprising a pinned photodiode.

6. An imaging device as in claim 1 further comprising a transfer gate between a photodiode charge collection accumulation area and a floating diffusion.

7. An imaging device as in claim 6 said transfer gate comprising a control input.

8. An imaging device as in claim 7 wherein said control input is set to establish a threshold potential at which charge overflow occurs.

9. An imaging device in claim 8 wherein charge overflow is from said photodiode to said floating diffusion.

10. An imaging device as in claim 6 wherein minimal charge is lost from said photodiode when charge overflow is not detected.

11. An imaging device as in claim 1 wherein a new integration period is initiated for said pixel at least partially in response to detection of charge overflow for said pixel.

12. An imaging device as in claim 1 wherein an integration period in progress for a pixel is continued at least partially in response to non-detection of charge overflow for said pixel.

13. An imaging device as in claim 10 wherein an integration period is selected at least partially in response to non-detection of charge overflow for said pixel.

14. An imaging device as in claim 8 wherein the charge overflow threshold potential is set to balance under utilization of a pixel full scale range against overly high occurrence of pixel value saturation at readout.

15. An imaging device as in claim 4 wherein the charge overflow detection reading is compared against an overflow detection threshold.

16. An imaging device as in claim 4 wherein an overflow detection threshold is set to balance reliable overflow detection against unnecessarily high loss of charge from the pixel at the detection threshold.

17. An imaging device as in claim 1 further comprising anti-blooming control.

18. An imaging device as in claim 1 further comprising a shared readout node configured to reduce a per pixel transistor count.

19. An imaging device as in claim 1 wherein said overflow detection circuit is associated with a corresponding column readout line.

20. An imaging device as in claim 1 comprising 450 and more rows and 750 and more columns.

21. An imaging device as in claim 1 further comprising a row transfer gate enable and control line.

22. An imaging device as in claim 1 formed on a silicon substrate, wherein pixel readout circuits are placed on an opposing side of said array of pixels relative to integration period selection circuits.

23. An imaging device, comprising:

an array of pixels formed on a silicon substrate, wherein pixel readout circuits are placed on an opposing side of said array of pixels relative to integration period selection circuits.

24. An imaging device as in claim 23 further comprising overflow detection circuit configured to dynamically determine an integration period for at least one pixel.

25. An imaging device as in claim 23 further comprising compensation for charge loss.

26. An imaging device as in claim 23 further comprising correlated double sampling for final readout of a pixel value.

27. An imaging device as in claim 23 further comprising correlated double sampling for the charge overflow detection reading.

28. An imaging device as in claim 23 further comprising a 4 transistor based pixel design comprising a pinned photodiode.

29. An imaging device as in claim 23 further comprising a transfer gate between a photodiode charge collection accumulation area and a floating diffusion.

30. An imaging device as in claim 23 further comprising a transfer gate comprising a control input.

31. An imaging device as in claim 23 further comprising anti-blooming control.

32. An imaging device as in claim 23 further comprising a shared readout node configured to reduce a per pixel transistor count.

33. An imaging device as in claim 24 wherein said overflow detection circuit is associated with a corresponding column readout line.

34. An imaging device as in claim 23 comprising 450 and more rows and 750 and more columns.

35. An imaging device as in claim 23 further comprising a row transfer gate enable and control line.

36. An imaging device, comprising:

an array of pixels based on a 4 transistor pixel design comprising a pinned photodiode and at least one charge overflow detection circuit configured to dynamically determine an integration period for at least one pixel.

37. An imaging device as in claim 36 further comprising compensation for charge loss.

38. An imaging device as in claim 36 further comprising correlated double sampling for final readout of a pixel value.

39. An imaging device as in claim 36 further comprising correlated double sampling for the charge overflow detection reading.

40. An imaging device as in claim 36 further comprising a transfer gate between a photodiode charge collection accumulation area and a floating diffusion.

41. An imaging device as in claim 36 further comprising a transfer gate comprising a control input.

42. An imaging device as in claim 36 further comprising anti-blooming control.

43. An imaging device as in claim 36 further comprising a shared readout node configured to reduce a per pixel transistor count.

44. An imaging device as in claim 36 wherein said overflow detection circuit is associated with a corresponding column readout line.

45. An imaging device as in claim 36 comprising 450 and more rows and 750 and more columns.

46. An imaging device as in claim 36 further comprising a row transfer gate enable and control line.

47. An imaging device as in claim 36 formed on a silicon substrate, wherein pixel readout circuits are placed on an opposing side of said array of pixels relative to integration period selection circuits.