Manufacturing Method of Semiconductor Device

• US 20100190293A1
• Filed: 07/18/2008
• Published: 07/29/2010
• Est. Priority Date: 07/23/2007
• Status: Active Grant

• Current Assignee: Lintec Corporation
• Original Assignee: Lintec Corporation
• Inventors: Maeda, Jun, Yamazaki, Osamu, Tanaka, Keiko
• Granted Patent: US 8,003,441 B2
• Time in Patent Office: Days
• US Class Current: 438/108
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/27436 Lamination of a preform, e.g. foil, sheet or layer
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73104 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81903 : by means of a layer connector
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83208 : applying unidirectional static pressure
• CPC Class Codes: H01L 2224/838 : Bonding techniques
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/90 : Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01088 : Radium [Ra]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

The present invention has been achieved reflecting such situation, and its object is to provide a manufacturing method of a semiconductor device capable of continuously performing the mounting process which applies a so-called DBG process and a flip chip bonding method, and can contribute to simplify the manufacturing process and to improve the reliability with no void in the product. The manufacturing method of a semiconductor device according to the present invention comprises:

• • laminating a surface protective sheet to a circuit surface side of a wafer formed with grooves which divide each circuit wherein an adhesive film is adhered on the circuit surface of the wafer;
  • reducing the thickness of the wafer and finally dividing the wafer into individual chips by grinding a back face of the wafer;
  • picking up individual chips together with the adhesive film;
  • die-bonding said individual chip to predetermined position of a chip mounting substrate via said adhesive film;
  • fixing the chip to the chip mounting substrate by heating the die-bonded chip having the adhesive film; and
  • applying a static pressure larger than an ambient pressure by 0.05 MPa or more to a stacked body including the adhesive film one or more times, at any point between adhering the wafer to the adhesive film and fixing the chip to the chip mounting substrate.

Claims

1. A manufacturing method of a semiconductor device comprising:

laminating a surface protective sheet to a circuit surface side of a wafer formed with grooves which divide each circuit wherein an adhesive film is adhered on the circuit surface of the wafer;

reducing the thickness of the wafer and finally dividing the wafer into individual chips by grinding a back face of the wafer;

picking up individual chips together with the adhesive film;

die-bonding said individual chip to predetermined position of a chip mounting substrate via said adhesive film;

fixing the chip to the chip mounting substrate by heating the die-bonded chip having the adhesive film; and

applying a static pressure larger than an ambient pressure by 0.05 MPa or more to a stacked body including the adhesive film one or more times, at any point between adhering the wafer to the adhesive film and fixing the chip to the chip mounting substrate.

2. The manufacturing method of a semiconductor device as set forth in claim 1 wherein the static pressure is applied after the die-bonding.

3. The manufacturing method of a semiconductor device as set forth in claim 1 wherein the chip is fixed to the chip mounting substrate while applying the static pressure.