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Method of Forming a MEMS Topped Integrated Circuit with a Stress Relief Layer

  • US 20100190311A1
  • Filed: 03/30/2010
  • Published: 07/29/2010
  • Est. Priority Date: 04/09/2008
  • Status: Active Grant
First Claim
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1. A method of forming a semiconductor wafer comprising:

  • forming a stress relief layer that touches a top surface of a passivation layer, the stress relief layer having a first maximum bulk elongation, the passivation layer being non-conductive, touching a conductive region, and having a second maximum bulk elongation; and

    forming a MEMS film that touches the stress relief layer, the MEMS film having a third maximum bulk elongation, the first maximum bulk elongation being substantially greater than the second maximum bulk elongation.

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