COMPUTER SYSTEM AND NETWORK INTERFACESUPPORTING CLASS OF SERVICE QUEUES
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Accused Products
Abstract
A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory. A data processing system, a method for management of a network interface and a network interface are also provided by the present invention that include an embedded firewall at the network interface level of the system, which protects against inside and-outside attacks on the security of data processing system. Furthermore, a data processing system, a method for management of a network interface and a network interface are a provided by the present invention that support class of service management for packets incoming from the network, by applying priority rules at the network interface level of the system.
76 Citations
95 Claims
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1-74. -74. (canceled)
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75. An integrated circuit for an interface in which packets are transferred between a network medium and a host bus system, the integrated circuit comprising:
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medium access control (MAC) unit through which data transferred at a data transfer rate of 100 Megabits per second or higher; a port, adapted to be coupled with the host bus system, through which data is transferred to and from the host bus system; buffer memory, coupled to the MAC unit and the port, storing packets in transit between the network medium and the host bus system; and logic, coupled with the buffer memory, to store a rule parameter, to access data fields in packets stored in the buffer, and to perform a logic function based on the accessed data fields and on the rule parameter, that produces a result used to determine a priority for transfer of corresponding packet out of the second port. - View Dependent Claims (76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 91)
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80-1. The integrated circuit of claim 75, wherein said rule parameter includes configuration values indicating a location of a field in the corresponding packet to be accessed.
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92. A data processing system, comprising:
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a processor; host memory; a host bus system coupled to the processor and the host memory; a network interface coupled to the host bus system, in which packets are transferred between a network medium and a host bus system, the network interface including; a first port adapted to be coupled to the network medium; a second port adapted to be coupled to the host bus system; buffer memory, having an incoming data path coupled to at least one of the first and second ports, storing packets in transit between the first and second ports; and logic, coupled with the buffer memory to access data fields in packets stored in the buffer memory, and to determine a priority for transfer of corresponding packet to the host bus system in response to the accessed data field. - View Dependent Claims (93, 94, 95)
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Specification