HOST CONTROLLER

• US 20100191874A1
• Filed: 01/26/2009
• Published: 07/29/2010
• Est. Priority Date: 01/26/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Galbo, Neal A., Radke, William H., Tsai, Victor Y., Leibowitz, Robert N., Feeley, Peter
• Granted Patent: US 8,327,040 B2
• Time in Patent Office: Days
• US Class Current: 710/24
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Claims

1. A method for controlling a memory device, comprising:

storing device class dependent information and a command in one or more of host system memory and host controller memory;

setting a pointer to the command in a register in a host controller;

directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and

executing the command with the memory device.

2. The method of claim 1, wherein directing access to the host system memory includes managing direct memory access (DMA) of data and providing flow control of data between a host and the memory device with a host controller.

3. The method of claim 2, wherein directing access to the host system memory includes managing DMA of data and providing flow control without host processor intervention.

4. The method of claim 1, wherein the method includes storing device class independent information in one or more registers in a host controller.

5. The method of claim 4, wherein storing device class independent information includes storing one or more types of information selected from the group including:

device control and interrupt information;

device enable/disable information;

device power state control/status information;

one or more pointers to device-class dependent information in the host system memory;

one or more pointers to commands in the host system memory;

a particular device class associated with a particular transaction layer register entry; and

a reset command.

6. The method of claim 4, wherein the command is written with small computer system interface (SCSI) protocol.

7. The method of claim 6, wherein the command is modified with the device class dependent information and the device class independent information.

8. The method of claim 1, wherein directing access to the one or more of host system memory and host controller memory with the memory device via the host controller includes providing access to a read command and a write command and executing the read command and write command with the memory device.

9. The method of claim 1, wherein the method includes associating the command with a segment identifier (SID) and wherein the SID identifies a base address in a SID map table for the memory device to write data to the one or more of host system memory and host controller memory based on the command.

10. The method of claim 9, wherein the SID identifies a base address in a SID map table for the memory device to read data from the one or more of host system memory and host controller memory based on the command.

12. The method of claim 1, wherein a peripheral device is coupled to the host controller via the hardware port.

13. The method of claim 12, wherein the peripheral device is selected from the group including:

a digital camera;

a digital music device;

a network device; and

a USB device.

11. A method for controlling a memory device, comprising:

storing device class dependent information and a command in one or more of host system memory and host controller memory;

setting a pointer to the command in a register in a host controller;

directing access to the one or more of host system memory and host controller memory with the memory device via the host controller;

executing the command with the memory device; and

transferring data between the memory device and a hardware port.

14. The method of claim 11, wherein the command causes data to be read from the memory device and written to the peripheral device.

15. The method of claim 11, wherein the command includes a segment identifier (SID) to indicate where data is written on the peripheral device.

16. The method of claim 11, wherein the command causes data to be read from the peripheral device and written to the memory device.

17. The method of claim 11, wherein the command includes a SID to indicate where data is read from on the peripheral device.

18. The method of claim 11, wherein a media codec is coupled to the host controller via the hardware part for audio and/or video play-back.

19. A method for operating a memory device, comprising:

storing device class independent information in one or more registers in a host controller;

storing device class dependent information in a memory array;

building a read command in the memory array with a host system processor;

sending the read command from the memory array to the memory device via a host system controller; and

initiating a direct memory access (DMA) write from the memory device to the memory array with the memory device.

20. The method of claim 19, wherein the method includes allocating data space in the memory array for the read command data with the host system processor;

setting an identifier associated with the read command with the host system processor, wherein the identifier indicates a location of the data space in the memory array for the read command data;

setting a memory pointer in a register with the host system processor, wherein the memory pointer indicates the location of the read command in the memory array.

21. The method of claim 20, wherein the identifier is a segment identifier (SID) and wherein the SID locates a base address in a SID table in the one or more of host system memory and host controller memory for the location of read command data.

22. The method of claim 21, wherein the SID indentifies a range of addresses in the one or more of host system memory and host controller memory indicating valid locations for the read command data.

23. The method of claim 20, wherein the method includes initiating a memory write to the data space allocated in the memory array at the location indicated by the identifier associated with the read command by the memory device.

24. The method of claim 19, wherein the memory array is a memory array type selected from the group including:

host system memory and host controller memory.

25. The method of claim 19, wherein the method includes updating the read command with a completion status in the memory array with the memory device.

26. The method of claim 19, wherein the method includes:

writing an interrupt to the register with the memory device;

interrupting the host system processor with the host system controller; and

reading the register with the host system processor to determine a reason for the interrupt.

27. A method for operating a memory device, comprising:

storing device class independent information in registers in a host controller;

storing device class dependent information in one or more of host system memory and host controller memory;

building a write command with a host system processor in one or more of host system memory and host controller memory;

notifying the memory device of the write command in the one or more of host system memory and host controller memory with the host system controller;

acting upon the notification of the write command by executing the write command with the memory device; and

initiating a direct memory access (DMA) read of write command data in the one or more of host system memory and host controller memory and returning the write command data to the memory device with the memory device.

28. The method of claim 27, wherein the method includes allocating space in one or more of host system memory and host controller memory for the write command data with the host system processor;

setting an identifier associated with the write command with the host system processor, where the identifier indicates a location of the data space for the write command data;

setting a memory pointer in a register with the host system processor, wherein the memory pointer indicates the location of the write command in one or more of host system memory and host controller memory.

29. The method of claim 28, wherein the identifier is a segment identifier (SID) and wherein the SID locates a base address in a SID table in the one or more of host system memory and host controller memory indicating the location of write command data.

30. The method of claim 29, wherein the SID indentifies a range of addresses in the one or more of host system memory and host controller memory indicating valid locations for the write command data.

31. The method of claim 27, wherein the method includes updating the write command with a completion status to the one or more of host system memory and host controller memory with the memory device.

32. A memory system, comprising:

one or more memory devices each coupled to at least one other of the one or more memory devices via a bus;

a host controller coupled to one or more of the memory devices;

a host processor, wherein the host controller is coupled to the host controller; and

system memory, wherein device class dependent information is stored in the system memory and the host controller transmits commands built by the host processor in the system memory to the one or more memory devices to read data from and/or write data to the one or more memory devices.

33. The system of claim 32, wherein the host controller transmits commands built by the host processor in the system memory to the number of memory devices to read data from and/or write data to the system memory at a base address in the system memory specified in the command.

34. The system of claim 32, wherein the host controller transmits commands built by the host processor in the system memory to the number of memory devices to read data from and/or write data to the number of memory devices at a base address in the system memory indicated by a segment identifier (SID).

35. The system of claim 32, wherein a SID table located in host controller memory indicates the base address in the system memory where to read data from and/or write data to in the system memory.

36. The system of claim 32, wherein a SID table located in host controller memory indicates a range of acceptable base addresses in the system memory where to read data from and/or write data to in the system memory.

37. The system of claim 36, wherein the SID is compared with the range of acceptable base addresses in the SID table to determine if a base address indicated by the SID in the command is valid.

38. The system of claim 32, wherein device class dependent information stored in the system memory is written to the system memory on power-up of the one or more memory devices.

39. The system of claim 32, wherein the one or more memory devices have device class independent information stored in one or more registers in a host controller and wherein each of the one or more registers has device class independent information that is associated with one of the one or more memory devices.

40. The system of claim 39, wherein device class independent information stored in the one or more registers is written to the registers on power-up of the one or more memory devices.

41. A memory system, comprising:

one or more memory devices each coupled to at least one other of the one or more memory devices via a bus;

a host controller, wherein the host controller includes host controller memory and is coupled to one or more of the memory devices;

a host processor, wherein the host processor is coupled to the host controller;

system memory, wherein device class dependent information is stored in the system memory and/or the host controller memory and the host controller transmits commands built by the host processor in the system memory and/or the host controller memory to the one or more memory devices to read data from and/or write data to the one or more memory devices.

42. The system of claim 41, wherein the host controller has a hardware port and a peripheral device is coupled to the hardware port.

43. The system of claim 42, wherein the host controller transmits commands built by the host processor in the system memory and/or the host controller memory to the number of memory devices to read data from and/or write data to the peripheral device.

44. The system of claim 41, wherein the host controller transmits commands built by the host processor in the system memory and/or the host controller memory to the number of memory devices to read data from and/or write data to system memory.

45. The system of claim 41, wherein the host controller transmits commands built by the host processor in the system memory and/or the host controller memory to the number of memory devices to read data from and/or write data to host controller memory.

46. The system of claim 41, wherein device class independent information is stored in one or more registers in system memory and/or host controller memory.

47. A host controller device, comprising:

a host controller coupled to one or more memory devices, a host processor, and system memory, wherein device class dependent information is stored in the system memory and/or host controller memory and the host controller transmits commands built by the host processor in the system memory to the number of memory devices to read data from and/or write data to the one or more memory devices.

48. The device of claim 47, wherein device class dependent information is information that indicates operating parameters that are specific to the memory device.

49. The device of claim 47, wherein the host processor runs a device driver to store device class independent information in the system memory and/or host controller memory.

50. The device of claim 49, wherein device class independent information is information that indicates operating parameters for memory devices independent of the device type.

51. The device of claim 47, wherein device class independent information is stored in one or more registers in system memory and/or host controller memory.