Monitoring Interrupt Acceptances in Guests

• US 20100191887A1
• Filed: 11/05/2009
• Published: 07/29/2010
• Est. Priority Date: 01/26/2009
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Serebrin, Benjamin C.
• Granted Patent: US 8,234,429 B2
• Time in Patent Office: Days
• US Class Current: 710/267
• CPC Class Codes: G06F 2009/45579 I/O management, e.g. providing access to device drivers or storage
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

In one embodiment, an interrupt acceptance control circuit is provided. The interrupt acceptance control circuit may monitor one or more guest interrupt controllers in a system in response to an IPI (or device interrupt) issued in a guest, to determine if each targeted vCPU in the guest has accepted the interrupt. If not, the interrupt acceptance control circuit may communicate the lack of acceptance to the VMM, in one embodiment. The VMM may attempt to schedule the vCPUs that have not accepted the interrupt, for example.

Claims

1. A node comprising:

one or more interrupt controllers, each interrupt controller associated with a respective processor in the node and configured to interrupt the respective processor in response to one or more interrupts in the interrupt controller, and wherein each interrupt controller is programmable with a guest identifier (ID) to identify an active guest in the respective processor; and

an interrupt acceptance control circuit coupled to the one or more interrupt controllers, wherein the interrupt acceptance control circuit is configured to monitor the one or more interrupt controllers for acceptance of an interrupt in a first guest, and wherein the interrupt comprises an indication of one or more targeted virtual processors in the first guest, and wherein the interrupt acceptance control circuit is configured to determine wherein or not each targeted virtual processor has accepted the interrupt.

2. The node as recited in claim 1 wherein the interrupt acceptance control circuit is configured to communicate to a virtual machine monitor responsive to at least one of the targeted virtual processors not accepting the interrupt.

3. The node as recited in claim 1 further configured to communicate the interrupt to at least one other node in a system, wherein one or more processors in the other node are configurable to execute portions of the first guest.

4. The node as recited in claim 3 wherein the other node is configured to return an interrupt response to the node, wherein the interrupt acceptance control circuit is configured to record interrupt acceptances indicated in the interrupt response packet.

5. The node as recited in claim 1 wherein the interrupt acceptance control circuit is configured to initialize a count of a number of targeted virtual processors in response to the interrupt.

6. The node as recited in claim 5 wherein the interrupt acceptance control circuit is configured decrement the count for each acceptance, and wherein the interrupt acceptance control circuit is configured to determine whether or not each targeted virtual processor has accepted the interrupt by comparing the count to zero.

7. The node as recited in claim 1 wherein the interrupt acceptance control circuit is configured to initialize a value identifying the targeted virtual processors in response to the interrupt.

8. The node as recited in claim 7 wherein the interrupt acceptance control circuit is configured to update the value to remove an indication of a first targeted virtual processor in response to acceptance of the interrupt by the interrupt controller corresponding to the first targeted virtual processor, and wherein the interrupt acceptance control circuit is configured to determine whether or not each targeted virtual processor has accepted the IPI by determining that the value identifies no more targeted virtual processors.

9. The node as recited in claim 1 wherein, in response to a physical broadcast interrupt, the interrupt acceptance control circuit is configured to read a data structure in memory to determine a number of virtual processors in the first guest, wherein the each virtual processor in the first guest is targeted by the physical broadcast interrupt.

10. A method comprising:

monitoring one or more interrupt controllers for acceptance of an interrupt issued in a first guest, wherein each interrupt controller is associated with a respective processor in a node and is configured to interrupt the respective processor in response to one or more interrupts in the interrupt controller, and wherein each interrupt controller is programmable with a guest identifier (ID) to identify an active guest in the respective processor, and wherein the interrupt indicates one or more targeted virtual processors in the first guest; and

communicating a lack of acceptance of the interrupt to a virtual machine monitor when at least one targeted virtual processor has not accepted the interrupt.

11. The method as recited in claim 10 further comprising communicating the interrupt to at least one other node in a system, wherein one or more processors in the other node are configurable to execute portions of the first guest.

12. The method as recited in claim 11 further comprising:

the other node returning an interrupt response to the node; and

recording interrupt acceptances indicated in the interrupt response in response to receiving the interrupt response.

13. The method as recited in claim 10 further comprising initializing a count of a number of targeted virtual processors in response to issuance of the interrupt.

14. The method as recited in claim 13 wherein the monitoring comprises decrementing the count for each acceptance, and wherein the determining that at least one targeted virtual processor has not accepted the interrupt comprises comparing the count to zero.

15. The method as recited in claim 10 further comprising initializing a value identifying the targeted virtual processors in response to issuance of the interrupt.

16. The method as recited in claim 15 wherein the monitoring comprises updating the value to remove an indication of a first targeted virtual processor in response to acceptance of the interrupt by the interrupt controller corresponding to the first targeted virtual processor, and wherein determining that at least one targeted virtual processor has not accepted the interrupt comprises determining that the value identifies at least one targeted virtual processor.

17. The method as recited in claim 10 further comprising determining that at least one targeted virtual processor has not accepted the interrupt, wherein the communicating is responsive to the determining.

18. A system comprising:

a first node including one or more first interrupt controllers and a first interrupt acceptance control circuit coupled to the one or more first interrupt controllers, wherein each first interrupt controller is associated with a respective processor in the first node and is configured to interrupt the respective processor in response to one or more interrupts in the interrupt controller, and wherein each interrupt controller is programmable with a guest identifier (ID) to identify an active guest in the respective processor, wherein the first interrupt acceptance control circuit, in response to a first interprocessor interrupt (IPI) from one of the one or more first interrupt controllers, is configured to issue a first interrupt message; and

a second node coupled to the first node, wherein the second node includes one or more second interrupt controllers and a second interrupt acceptance control circuit, and wherein the second interrupt acceptance control circuit, in response to the first interrupt message, is configured to issue the IPI to the one or more second interrupt controllers and to aggregate responses from the one or more second interrupt controllers, wherein the second node is configured to transmit an interrupt response to the first node to transmit the aggregate response to the IPI from the second node.

19. The system as recited in claim 18 wherein the aggregate response is a count of the number of interrupt acceptances.

20. The system as recited in claim 18 wherein the aggregate response identifies virtual processors within the guest that have accepted the interrupt.