Solid state drive controller with fast NVRAM buffer and non-volatile tables

• US 20100191896A1
• Filed: 01/23/2009
• Published: 07/29/2010
• Est. Priority Date: 01/23/2009
• Status: Active Application

• Current Assignee: Headway Technologies Incorporated
• Original Assignee: MagiQ Technologies, Incorporated
• Inventors: Kamigama, Takehiro, Murai, Takuma, Yang, Hsu Kai, Wang, Po-Kang
• Application Number:
  US12/321,663
• Publication Number:
  US 20100191896A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0873 Mapping of cache memory to specific storage devices or parts thereof
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

Systems and methods for a SSD controller enabling data transfer between a host and flash memories have been achieved. A major component of the SSD controller is a non-volatile buffer memory, which interfaces fast disk drive protocols and slow write and read cycles of NAND flash. Preferably MRAM or Phase Change RAM can be used for the buffer memory. Non-volatile tables can also be implemented for storing dynamic logical to physical address translation, defective sector information and their spare sectors and/or SSD configuration parameters. data are kept in a buffer memory when the buffer memory is not powered

Claims

1. A system to achieve a SSD controller supporting data transfer between a host and flash memory wherein data are kept in a buffer memory when the buffer memory is not powered comprising:

;

a CPU;

a CPU bus, connected to the CPU, a disk interface, a NVRAM cache buffer memory, a first-in-first out buffer, clock generators, and a flash interface;

said disk interface, supporting disk protocols, connected to said NVRAM cache buffer memory;

said NVRAM buffer cache memory, connected to said first-in-first-out buffer;

said first-in-first-out buffer, connected to a flash interface;

said flash interface; and

said clock generators, connected to said CPU bus, said disk interface, said NVRAM cache buffer, said first-in-first-out buffer (FIFO), and to said flash interface.

2. The system of claim 1 wherein said NVRAM buffer is a MRAM.

3. The system of claim 1 wherein said NVRAM buffer is a Phase Change RAM.

4. The system of claim 1 comprising at least one NVRAM table.

5. The system of claim 4 wherein said at least one NVRAM table is stored in a MRAM.

6. The system of claim 4 wherein said at least one NVRAM table is stored in a Phase Change RAM.

7. The system of claim 4 wherein logical to physical address translations are stored in one of said at least one NVRAM tables.

8. The system of claim 4 wherein defective sectors of Flash memory and their replacements are stored in one of said at least one NVRAM tables.

9. The system of claim 4 wherein SSD configuration parameters are stored in one of said at least one NVRAM tables.

10. A method to achieve a SSD controller supporting data transfer between a host and flash memory wherein data are kept in a buffer memory when the buffer memory is not powered comprising the steps of:

(1) providing a SSD controller comprising a CPU, a CPU bus, a disk interface, a NVRAM cache buffer, a first-in-first-out buffer (FIFO), and a flash interface;

(2) implementing in said CPU NVRAM control code;

(3) implementing said NVRAM for buffer cache memory; and

(4) operating said SSD.

11. The method of claim 10 wherein said NVRAM buffer is a MRAM.

12. The method of claim 10 wherein said NVRAM buffer is a Phase Change RAM.

13. The method of claim 10 wherein said SSD comprises at least one NVRAM table.

14. The method of claim 13 wherein logical to physical address translations are stored in one of said at least one NVRAM tables.

15. The method of claim 13 wherein defective sectors of Flash memory and their replacements are stored in one of said at least one NVRAM tables.

16. The method of claim 13 wherein SSD configuration parameters are stored in one of said at least one NVRAM tables.