System-On-A-Chip Having an Array of Programmable Processing Elements Linked By an On-Chip Network with Distributed On-Chip Shared Memory and External Shared Memory
First Claim
1. An integrated circuit comprising:
- an array of programmable processing elements linked by an on-chip communication network, each processing element including a plurality of processing cores and a local memory; and
a memory interface block, operably coupled to external memory and the on-chip communication network, for accessing the external memory in response to messages communicated from the processing elements of the array over the on-chip communication network;
wherein a portion of the local memory for a plurality of the processing elements of the array as well as a portion of the external memory are both allocated to store data shared by a plurality of processing elements of the array during execution of programmed operations distributed thereon.
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Abstract
An integrated circuit having an array of programmable processing elements and a memory interface linked by an on-chip communication network. Each processing element includes a plurality of processing cores and a local memory. The memory interface block is operably coupled to external memory and to the on-chip communication network. The memory interface supports accessing the external memory in response to messages communicated from the processing elements of the array over the on-chip communication network. A portion of the local memory for a plurality of the processing elements of the array as well as a portion of the external memory are both allocated to store data shared by a plurality of processing elements of the array during execution of programmed operations distributed thereon.
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Citations
14 Claims
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1. An integrated circuit comprising:
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an array of programmable processing elements linked by an on-chip communication network, each processing element including a plurality of processing cores and a local memory; and a memory interface block, operably coupled to external memory and the on-chip communication network, for accessing the external memory in response to messages communicated from the processing elements of the array over the on-chip communication network; wherein a portion of the local memory for a plurality of the processing elements of the array as well as a portion of the external memory are both allocated to store data shared by a plurality of processing elements of the array during execution of programmed operations distributed thereon. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification