Optimizing A Cache Back Invalidation Policy
First Claim
1. In a data processing system having one or more processors and multiple levels of cache, including a lower level cache and a higher level cache, a method comprising:
- detecting a data request at the lower level cache;
in response to a cache miss in the lower level cache, selecting a cache-line for eviction based upon (a) the presence bits and (b) the less recently used (LRU) bits;
determining whether a copy of the cache-line selected for eviction is present in a higher level cache;
when the copy of the cache-line selected for eviction is present in the higher level cache, invalidating the copy of the cache-line selected for eviction; and
updating the pseudo-LRU bits.
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Accused Products
Abstract
A method and a system for utilizing less recently used (LRU) bits and presence bits in selecting cache-lines for eviction from a lower level cache in a processor-memory sub-system. A cache back invalidation (CBI) logic utilizes LRU bits to evict only cache-lines within a LRU group, following a cache miss in the lower level cache. In addition, the CBI logic uses presence bits to (a) indicate whether a cache-line in a lower level cache is also present in a higher level cache and (b) evict only cache-lines in the lower level cache that are not present in a corresponding higher level cache. However, when the lower level cache-line selected for eviction is also present in any higher level cache, CBI logic invalidates the cache-line in the higher level cache. The CBI logic appropriately updates the values of presence bits and LRU bits, following evictions and invalidations.
57 Citations
15 Claims
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1. In a data processing system having one or more processors and multiple levels of cache, including a lower level cache and a higher level cache, a method comprising:
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detecting a data request at the lower level cache; in response to a cache miss in the lower level cache, selecting a cache-line for eviction based upon (a) the presence bits and (b) the less recently used (LRU) bits; determining whether a copy of the cache-line selected for eviction is present in a higher level cache; when the copy of the cache-line selected for eviction is present in the higher level cache, invalidating the copy of the cache-line selected for eviction; and updating the pseudo-LRU bits. - View Dependent Claims (2, 3, 4, 5)
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6. A data processing system comprising:
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one or more processors; a cache memory system hierarchically organized into multiple levels including a highest level having one or more level 1 caches and a lower adjacent level having one or more level 2 caches; the level 1 cache dedicated to one processor core or shared by multiple cores; a cache controller; a logic which when executed on the processor provides the functions of; detecting a data request at the lower level cache; in response to a cache miss in the lower level cache, selecting a cache-line for eviction based upon (a) the presence bits and (b) the less recently used (LRU) bits; determining whether a copy of the cache-line selected for eviction is present in a higher level cache; when the copy of the cache-line selected for eviction is present in the higher level cache, invalidating the copy of the cache-line selected for eviction; and updating the pseudo-LRU bits. - View Dependent Claims (7, 8, 9, 10)
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11. A processor chip comprising:
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one or more processors each having a higher level cache; a lower level cache associated with one or more higher level caches; and a cache controller which includes logic that executes to perform the following functions; detecting a data request at the lower level cache; in response to a cache miss in the lower level cache, selecting a cache-line for eviction based upon (a) the presence bits and (b) the less recently used (LRU) bits; determining whether a copy of the cache-line selected for eviction is present in a higher level cache; when the copy of the cache-line selected for eviction is present in the higher level cache, invalidating the copy of the cache-line selected for eviction; and updating the pseudo-LRU bits. - View Dependent Claims (12, 13, 14, 15)
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Specification