Providing Address Range Coherency Capability To A Device

• US 20100191920A1
• Filed: 01/27/2009
• Published: 07/29/2010
• Est. Priority Date: 01/27/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Harriman, David J., Fang, Zhen, Leddige, Michael W.
• Granted Patent: US 8,631,208 B2
• Time in Patent Office: Days
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Abstract

In one embodiment, the present invention includes a method for receiving a memory request from a device coupled to an input/output (IO) interconnect, accessing a mapping table associated with the IO interconnect to determine if an address range including an address of the memory request is coherent, and if so, sending the memory request and a coherency indicator to indicate the coherent state of data at the address, otherwise sending the memory request and the coherency indicator to indicate a non-coherent state. Other embodiments are described and claimed.

Claims

1. A method comprising:

receiving a memory request from a device coupled to a downstream side of an input/output (IO) interconnect;

accessing a first buffer associated with the IO interconnect to determine if an entry corresponding to an address of the memory request is present therein; and

if so, obtaining a coherency indicator from the entry and sending the memory request and the coherency indicator to a coherent interconnect coupled to an upstream side of the IO interconnect, the coherency indicator to indicate a coherency status of data associated with the memory request.

2. The method of claim 1, further comprising if the entry is not present, generating a miss request to request the entry from a second buffer of a core coupled to the coherent interconnect, and sending the miss request to the coherent interconnect.

3. The method of claim 2, further comprising receiving at least a portion of the entry from the second buffer and storing the coherency indicator in the first buffer.

4. The method of claim 3, further comprising prefetching at least a portion of at least one additional entry from the second buffer and storing at least one additional coherency indicator in the first buffer, the at least one additional entry corresponding to an address sequential to the address of the memory request.

5. The method of claim 1, wherein the memory request received from the device does not include any coherency information.

6. The method of claim 5, further comprising disabling the first buffer, and receiving the memory request in the IO interconnect from the device with a coherency hint to indicate the coherency status of the data.

7. The method of claim 1, further comprising receiving the memory request and the coherency indicator in the coherent interconnect and using the coherency indicator to handle the memory request.

8. The method of claim 7, further comprising sending a snoop request for the address of the memory request to at least one cache if the coherency status is indicative of a coherent status and stalling the memory request in the coherent interconnect until receipt of a snoop response to the snoop request.

9. The method of claim 7, further comprising sending the memory request directly to a memory coupled to the coherent interconnect if the coherency status is indicative of a non-coherent status.

10. An apparatus comprising:

a core to execute instructions and including a translation lookaside buffer (TLB), the TLB including a plurality of entries each having a translation field to map a virtual address to a physical address and a coherency field to store a coherency indicator that indicates a coherency state of a memory page corresponding to the entry;

a coherent interconnect coupled to the core;

an input/output (IO) interconnect coupled to the coherent interconnect, the IO interconnect including a coherency-TLB (c-TLB) including a plurality of entries each having an address field and a coherence field to store a coherency indicator from a corresponding entry of the TLB; and

at least one device coupled to the IO interconnect to provide a memory request to the IO interconnect, the IO interconnect to access the c-TLB to obtain a coherency indicator if an entry corresponding to the memory request is present therein, the memory request and the coherency indicator to be forwarded from the IO interconnect into the coherent interconnect.

11. The apparatus of claim 10, wherein the at least one device is to generate the memory request without an indication of coherency.

12. The apparatus of claim 10, wherein the apparatus comprises a system on a chip (SoC) formed on a single semiconductor die, and the at least one device comprises an intellectual property (IP) block.

13. The apparatus of claim 10, wherein the IO interconnect is to generate a miss request to request the entry from the TLB, and send the miss request to the coherent interconnect.

14. The apparatus of claim 13, wherein the IO interconnect is to receive at least a portion of the entry from the TLB and store the coherency indicator of the entry in a corresponding entry of the c-TLB.

15. The apparatus of claim 14, wherein each entry of the TLB further includes a cacheability field to store a cacheability indicator that indicates whether the memory page can be cached.

16. The apparatus of claim 15, wherein the IO interconnect is to receive the entry portion from the TLB and store the cacheability indicator in a corresponding entry of the c-TLB.

17. The apparatus of claim 11, further comprising a second TLB in the IO interconnect, the second TLB including a plurality of entries each having a translation field to map a virtual address to a physical address.

18. A system comprising:

a first integrated circuit including;

at least one core to execute instructions and including a memory management unit (MMU) to map a virtual address for a memory location to a physical address and to associate a coherency indicator with the memory location that indicates a coherency state of the memory location on an address range basis;

a first coherent interconnect coupled to the core;

a first input/output (IO) interconnect coupled to the first coherent interconnect, the first IO interconnect including a storage to store the coherency indicator associated with the memory location; and

at least one device coupled to the first IO interconnect to provide a memory request for the memory location to the first IO interconnect, the first IO interconnect to access the storage to obtain the coherency indicator and forward memory request and the coherency indicator to the first coherent interconnect, wherein the at least one device is to provide the memory request to the first IO interconnect without coherency information; and

a second integrated circuit coupled to the first integrated circuit via an inter-chip interconnect, wherein the second integrated circuit includes at least one peripheral device coupled to a second IO interconnect.

19. The system of claim 18, wherein the first IO interconnect is to generate a miss request to request the coherency indicator from the MMU if not present in the storage, and send the miss request to the first coherent interconnect.

20. The system of claim 18, wherein the storage is to store at least one memory type range register to indicate the coherency state of the address range including the memory location.