VOLTAGE-BASED MEMORY SIZE SCALING IN A DATA PROCESSING SYSTEM
First Claim
1. A method of using a memory, comprising:
- accessing a memory with a power supply voltage applied to the memory at a first value;
reducing the power supply voltage to a second value;
identifying a first portion of the memory as being non-functional, wherein the being non-functional is caused by the power supply voltage being at the second value;
accessing the memory exclusive of the first portion;
increasing the power supply voltage to a third value;
identifying a second portion of the first portion that is functional with the power supply being applied at the third value; and
accessing the memory including the second portion.
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Accused Products
Abstract
A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that include non-functional bits are not used. Much of the memory may remain functional and use is retained. When the voltage is increased, the portions of the memory that were not used because of being non-functional due to the reduced power supply voltage may then be used again. This is particularly useful in a cache where the decrease in available memory due to power supply voltage reduction can be implemented as a reduction in the number of ways. Thus, for example an eight way cache can simply be reduced to a four way cache when the power is being reduced or endurance increased.
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Citations
20 Claims
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1. A method of using a memory, comprising:
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accessing a memory with a power supply voltage applied to the memory at a first value; reducing the power supply voltage to a second value; identifying a first portion of the memory as being non-functional, wherein the being non-functional is caused by the power supply voltage being at the second value; accessing the memory exclusive of the first portion; increasing the power supply voltage to a third value; identifying a second portion of the first portion that is functional with the power supply being applied at the third value; and accessing the memory including the second portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of operating a system with a cache having a plurality of ways, comprising:
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operating the cache with a power supply voltage applied at a first value according to an allocation policy; asserting a request to decrease the power supply voltage to a second value; identifying a first set of ways of the plurality of ways that need to be disabled based on the power supply voltage being at the second value; masking out the first set of ways from the allocation policy; applying the power supply voltage at the second value; operating the cache with the power supply voltage applied at the second value according to the allocation policy with the first set of ways masked out; applying the power supply voltage at a third value greater than the second value; identifying a second set of ways from the first set of ways that can be added based on the power supply being applied at the third value; adding the second set of ways to the allocation policy; operating the cache with the power supply voltage applied at the third value according to the allocation policy with the second set of ways added. - View Dependent Claims (12, 13, 14, 15)
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16. A system, comprising:
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a cache controller; a cache coupled to the cache controller that has a plurality of ways, operates according to an allocation policy, and is powered by a power supply voltage; and a processor coupled to the cache and the cache controller, wherein; the cache controller responds to a request generated by the processor to decrease the power supply voltage applied to the cache by identifying a first set of ways and masking the first set of ways from the allocation policy; and the cache receives the reduced power supply voltage, is accessed by the processor exclusive of first set of ways, receives an increased power supply voltage after being accessed by the processor while receiving the reduced power supply voltage, and has a second set of ways from the first set of ways accessible by the processor while the cache is powered by the increased power supply voltage. - View Dependent Claims (17, 18, 19, 20)
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Specification