TRANSISTOR AND METHOD FOR MANUFACTURING THE TRANSISTOR

• US 20100193782A1
• Filed: 01/20/2010
• Published: 08/05/2010
• Est. Priority Date: 02/05/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: SAKATA, Junichiro
• Granted Patent: US 8,367,486 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

It is an object to reduce characteristic variation among transistors and reduce contact resistance between an oxide semiconductor layer and a source electrode layer and a drain electrode layer, in a transistor where the oxide semiconductor layer is used as a channel layer. In a transistor where an oxide semiconductor is used as a channel layer, at least an amorphous structure is included in a region of an oxide semiconductor layer between a source electrode layer and a drain electrode layer, where a channel is to be formed, and a crystal structure is included in a region of the oxide semiconductor layer which is electrically connected to an external portion such as the source electrode layer and the drain electrode layer.

Claims

1. A transistor comprising:

a gate electrode;

a gate insulating layer;

a source electrode layer and a drain electrode layer;

a first metal oxide layer electrically connected to the source electrode layer;

a second metal oxide layer electrically connected to the drain electrode layer; and

an oxide semiconductor layer having an amorphous structure overlapping with the gate electrode with the gate insulating layer interposed between the oxide semiconductor layer and the gate electrode,

wherein at least a first region in contact with the first metal oxide layer and a second region in contact with the second metal oxide layer in the oxide semiconductor layer each has a crystal structure.

2. The transistor according to claim 1, wherein each of the first metal oxide layer and the second metal oxide layer has a crystal structure.

3. The transistor according to claim 1,

wherein each of the first metal oxide layer, the second metal oxide layer, and the oxide semiconductor layer includes zinc, and

wherein a composition of the first metal oxide layer and the second metal oxide layer is different from a composition of the oxide semiconductor layer.

4. The transistor according to claim 1,

wherein each of the first metal oxide layer and the second metal oxide layer includes zinc oxide, and

wherein the oxide semiconductor layer is an oxide semiconductor layer including indium, zinc, and gallium.

5. The transistor according to claim 1,

wherein the first region and the second region include more zinc than other portion in the oxide semiconductor layer.

6. The transistor according to claim 1,

wherein a portion of the oxide semiconductor layer located between the source electrode layer and the drain electrode layer has an amorphous structure.

7. The transistor according to claim 1,

wherein a portion of the oxide semiconductor layer located to overlap with the gate electrode has an amorphous structure.

8. A transistor comprising:

a gate electrode over a substrate;

a gate insulating layer over the gate electrode;

a source electrode layer and a drain electrode layer over the gate insulating layer;

a first metal oxide layer over the source electrode layer;

a second metal oxide layer over the drain electrode layer; and

an oxide semiconductor layer having an amorphous structure overlapping with the gate electrode with the gate insulating layer interposed between the oxide semiconductor layer and the gate electrode and on the first metal oxide layer and the second metal oxide layer,

wherein at least a first region in contact with the first metal oxide layer and a second region in contact with the second metal oxide layer in the oxide semiconductor layer each has a crystal structure.

9. The transistor according to claim 8, wherein each of the first metal oxide layer and the second metal oxide layer has a crystal structure.

10. The transistor according to claim 8,

wherein each of the first metal oxide layer, the second metal oxide layer, and the oxide semiconductor layer includes zinc, and

wherein a composition of the first metal oxide layer and the second metal oxide layer is different from a composition of the oxide semiconductor layer.

11. The transistor according to claim 8,

wherein each of the first metal oxide layer and the second metal oxide layer includes zinc oxide, and

wherein the oxide semiconductor layer is an oxide semiconductor layer including indium, zinc, and gallium.

12. The transistor according to claim 8,

wherein the first region and the second region include more zinc than other portion in the oxide semiconductor layer.

13. The transistor according to claim 8,

wherein a portion of the oxide semiconductor layer located between the source electrode layer and the drain electrode layer has an amorphous structure.

14. The transistor according to claim 8,

wherein a portion of the oxide semiconductor layer located to overlap with the gate electrode has an amorphous structure.

15. A transistor comprising:

a gate electrode over a substrate;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer having an amorphous structure over the gate insulating layer;

a first metal oxide layer and a second metal oxide layer on the oxide semiconductor layer;

a source electrode layer over the first metal oxide layer; and

a drain electrode layer over the second metal oxide layer,

wherein at least a first region in contact with the first metal oxide layer and a second region in contact with the second metal oxide layer in the oxide semiconductor layer each has a crystal structure.

16. The transistor according to claim 15, wherein each of the first metal oxide layer and the second metal oxide layer has a crystal structure.

17. The transistor according to claim 15,

wherein each of the first metal oxide layer, the second metal oxide layer, and the oxide semiconductor layer includes zinc, and

wherein a composition of the first metal oxide layer and the second metal oxide layer is different from a composition of the oxide semiconductor layer.

18. The transistor according to claim 15,

wherein each of the first metal oxide layer and the second metal oxide layer includes zinc oxide, and

wherein the oxide semiconductor layer is an oxide semiconductor layer including indium, zinc, and gallium.

19. The transistor according to claim 15,

wherein the first region and the second region include more zinc than other portion in the oxide semiconductor layer.

20. The transistor according to claim 15,

wherein a portion of the oxide semiconductor layer located between the source electrode layer and the drain electrode layer has an amorphous structure.

21. The transistor according to claim 15,

wherein a portion of the oxide semiconductor layer located to overlap with the gate electrode has an amorphous structure.

22. A transistor comprising:

a source electrode layer and a drain electrode layer over a substrate;

a first metal oxide layer over the source electrode layer;

a second metal oxide layer over the drain electrode layer;

an oxide semiconductor layer having an amorphous structure on the first metal oxide layer and the second metal oxide layer,

a gate insulating layer over the oxide semiconductor layer; and

a gate electrode over the gate insulating layer overlapping with the oxide semiconductor layer,

wherein at least a first region in contact with the first metal oxide layer and a second region in contact with the second metal oxide layer in the oxide semiconductor layer each has a crystal structure.

23. The transistor according to claim 22, wherein each of the first metal oxide layer and the second metal oxide layer has a crystal structure.

24. The transistor according to claim 22,

wherein each of the first metal oxide layer, the second metal oxide layer, and the oxide semiconductor layer includes zinc, and

wherein a composition of the first metal oxide layer and the second metal oxide layer is different from a composition of the oxide semiconductor layer.

25. The transistor according to claim 22,

wherein each of the first metal oxide layer and the second metal oxide layer includes zinc oxide, and

wherein the oxide semiconductor layer is an oxide semiconductor layer including indium, zinc, and gallium.

26. The transistor according to claim 22,

wherein the first region and the second region include more zinc than other portion in the oxide semiconductor layer.

27. The transistor according to claim 22,

wherein a portion of the oxide semiconductor layer located between the source electrode layer and the drain electrode layer has an amorphous structure.

28. The transistor according to claim 22,

wherein a portion of the oxide semiconductor layer located to overlap with the gate electrode has an amorphous structure.

29. A method for manufacturing a transistor comprising the steps of:

forming a gate electrode over a substrate;

forming a gate insulating layer over the gate electrode;

forming a source electrode layer and a drain electrode layer over the gate insulating layer;

forming a first metal oxide layer including zinc and a crystal structure over the source electrode layer;

forming a second metal oxide layer including zinc and a crystal structure over the drain electrode layer;

forming an oxide semiconductor layer including zinc and an amorphous structure over the gate electrode and on the first metal oxide layer and the second metal oxide layer; and

performing heat treatment to move zinc from the first metal oxide layer and the second metal oxide layer to the oxide semiconductor layer such that a first region in contact with the first metal oxide layer and a second region in contact with the second metal oxide layer are crystallized in the oxide semiconductor layer.

30. The method for manufacturing the transistor according to claim 29,

wherein the oxide semiconductor layer is formed using a composition different from a composition of the first metal oxide layer and the second metal oxide layer.

31. The method for manufacturing the transistor according to claim 29,

wherein the first metal oxide layer and the second metal oxide layer are formed using zinc oxide, and

wherein the oxide semiconductor layer is formed using an oxide semiconductor layer including indium, zinc, and gallium.

32. The method for manufacturing the transistor according to claim 29,

wherein the oxide semiconductor layer is formed by a sputtering method using a target including indium, gallium, and zinc.

33. The method for manufacturing the transistor according to claim 29,

wherein a portion of the oxide semiconductor layer located between the source electrode layer and the drain electrode layer is kept amorphous in the performing heat treatment step.

34. The method for manufacturing the transistor according to claim 29,

wherein a portion of the oxide semiconductor layer located to overlap with the gate electrode is kept amorphous in the performing heat treatment step.

35. A method for manufacturing a transistor comprising the steps of:

forming a gate electrode over a substrate;

forming a gate insulating layer over the gate electrode;

forming an oxide semiconductor layer including zinc and an amorphous structure over the gate insulating layer;

forming a first metal oxide layer and a second metal oxide layer each including zinc and a crystal structure over the oxide semiconductor layer;

forming a source electrode layer over the first metal oxide layer;

forming a drain electrode layer over the second metal oxide layer; and

performing heat treatment to move zinc from the first metal oxide layer and the second metal oxide layer to the oxide semiconductor layer such that a first region in contact with the first metal oxide layer and a second region in contact with the second metal oxide layer are crystallized in the oxide semiconductor layer.

36. The method for manufacturing the transistor according to claim 35,

wherein the oxide semiconductor layer is formed using a composition different from a composition of the first metal oxide layer and the second metal oxide layer.

37. The method for manufacturing the transistor according to claim 35,

wherein the first metal oxide layer and the second metal oxide layer are formed using zinc oxide, and

wherein the oxide semiconductor layer is formed using an oxide semiconductor layer including indium, zinc, and gallium.

38. The method for manufacturing the transistor according to claim 35,

wherein the oxide semiconductor layer is formed by a sputtering method using a target including indium, gallium, and zinc.

39. The method for manufacturing the transistor according to claim 35,

wherein a portion of the oxide semiconductor layer located between the source electrode layer and the drain electrode layer is kept amorphous in the performing heat treatment step.

40. The method for manufacturing the transistor according to claim 35,

wherein a portion of the oxide semiconductor layer located to overlap with the gate electrode is kept amorphous in the performing heat treatment step.

41. A method for manufacturing a transistor comprising the steps of:

forming a source electrode layer and a drain electrode layer over a substrate;

forming a first metal oxide layer including zinc and a crystal structure over the source electrode layer;

forming a second metal oxide layer including zinc and a crystal structure over the drain electrode layer;

forming an oxide semiconductor layer including zinc and an amorphous structure on the first metal oxide layer and the second metal oxide layer;

performing heat treatment to move zinc from the first metal oxide layer and the second metal oxide layer to the oxide semiconductor layer such that a first region in contact with the first metal oxide layer and a second region in contact with the second metal oxide layer are crystallized in the oxide semiconductor layer;

forming a gate insulating layer over the oxide semiconductor layer; and

forming a gate electrode over the gate insulating layer overlapping the oxide semiconductor layer.

42. The method for manufacturing the transistor according to claim 41,

wherein the oxide semiconductor layer is formed using a composition different from a composition of the first metal oxide layer and the second metal oxide layer.

43. The method for manufacturing the transistor according to claim 41,

wherein the first metal oxide layer and the second metal oxide layer are formed using zinc oxide, and

wherein the oxide semiconductor layer is formed using an oxide semiconductor layer including indium, zinc, and gallium.

44. The method for manufacturing the transistor according to claim 41,

wherein the oxide semiconductor layer is formed by a sputtering method using a target including indium, gallium, and zinc.

45. The method for manufacturing the transistor according to claim 41,

wherein a portion of the oxide semiconductor layer located between the source electrode layer and the drain electrode layer is kept amorphous in the performing heat treatment step.

46. The method for manufacturing the transistor according to claim 41,

wherein a portion of the oxide semiconductor layer located to overlap with the gate electrode is kept amorphous in the performing heat treatment step.