SEMICONDUCTOR DEVICE

• US 20100193836A1
• Filed: 05/12/2009
• Published: 08/05/2010
• Est. Priority Date: 02/02/2009
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Kusunoki, Shigeru, Okuno, Takahiro
• Granted Patent: US 7,800,183 B2
• Time in Patent Office: Days
• US Class Current: 257/139
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device includes a substrate of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a collector region of the second conductivity type, a trench gate, which is formed in a trench via a gate insulation film, an electrically conductive layer, which is formed within a contact trench that is formed through the source region, a source electrode, which is in contact with the electrically conductive layer and the source region, and a latch-up suppression region of the second conductivity type, which is formed within the base region, in contact with the electrically conductive layer, and higher in impurity concentration than the base region. The distance between the gate insulation film and the latch-up suppression region is not less than the maximum width of a depletion layer that is formed in the base layer by the trench gate.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a base region of a second conductivity type, which is formed on the front surface of the semiconductor substrate;

a source region of the first conductivity type, which is formed on the front surface of the base region;

a collector region of the second conductivity type, which is formed on the back surface of the semiconductor substrate;

a trench gate, which is formed in a trench via a gate insulation film, the trench being formed through the source region and the base region;

an electrically conductive layer, which is formed within a contact trench that is formed through the source region;

a source electrode, which is in contact with the electrically conductive layer and the source region; and

a latch-up suppression region of the second conductivity type, which is formed within the base region, in contact with the electrically conductive layer, and higher in impurity concentration than the base region;

wherein the distance between the gate insulation film and the latch-up suppression region is not less than the maximum width of a depletion layer that is formed in the base layer by the trench gate.

2. The semiconductor device according to claim 1, wherein the contact trench is deep enough to reach the base region.

3. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a base region of a second conductivity type, which is formed on the front surface of the semiconductor substrate;

a source region of the first conductivity type, which is formed on the front surface of the base region;

a high-concentration impurity region of the second conductivity type, which is formed on the front surface of the base region, in contact with the source region, and higher in impurity concentration than the base region;

a collector region of the second conductivity type, which is formed on the back surface of the semiconductor substrate;

a trench gate, which is formed in a trench via a gate insulation film, the trench being formed within the base region through the source region;

a dummy trench, which is formed in parallel with the trench gate and positioned toward the trench gate rather than toward the high-concentration impurity region; and

a source electrode, which is in contact with the high-concentration impurity region and the source region;

wherein the dummy trench is provided with a break.

4. The semiconductor device according to claim 3, wherein the source region is extended to reach the break in the dummy trench.

5. The semiconductor device according to claim 3, wherein the dummy trench is deep enough to reach the interface between the base region and the semiconductor substrate.