SUBSTRATE BAND GAP ENGINEERED MULTI-GATE PMOS DEVICES

• US 20100193840A1
• Filed: 04/09/2010
• Published: 08/05/2010
• Est. Priority Date: 03/29/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jin, Been-Yih, Kavalieros, Jack T., Doyle, Brian S., Datta, Suman
• Granted Patent: US 8,169,027 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.

Claims

1. A multi-gate transistor comprising:

a fin having an upper portion and a lower portion, said upper portion having a first band gap and said lower portion having a second band gap, larger than said first band gap to inhibit current flow from said upper portion to said lower portion;

a gate structure electrically coupled with said upper portion and said lower portion, the gate structure including a gate dielectric in direct contact with a sidewall of the upper and lower portions of the fin;

a source and drain region in the fin, wherein the source and drain regions are fully contained within the upper portion of the fin; and

a substrate positioned below said fin.

2. The multi-gate transistor of claim 1 wherein said first band gap is at least 0.3 electron volts narrower than said second band gap and wherein the difference in the band gap creates a band gap offset between the valence bands of the upper and lower portions of the fin.

3. The multi-gate transistor of claim 1 wherein said gate structure includes a top portion positioned over said fin.

4. The multi-gate transistor of claim 1 wherein said lower portion is formed from said substrate.

5. The multi-gate transistor of claim 1 wherein a channel portion of the upper portion between the source and drain regions is undoped.

6. The multi-gate transistor of claim 1 further comprising an insulator positioned between said fin and said substrate.

7. The multi-gate transistor of claim 2 wherein said upper portion is composed of silicon-germanium having approximately 30 atomic percent of germanium.

8. The multi-gate transistor of claim 4 wherein said second band gap is 0.4 electron volts wider than said first band gap.

9. The multi-gate transistor of claim 6 wherein said insulator is formed using a bonded semiconductor-on-insulator (SOI) technique.

10. A multi-gate transistor comprising:

an upper portion having a first band gap, said upper portion fully containing a source region and a drain region of the transistor;

a lower portion having a second band gap wider than said first band gap and positioned below said upper portion to form a fin;

a gate structure having a first portion and a second portion, said first portion and second portion positioned on opposing sides of said fin and disposed over an undoped channel of said transistor, the gate structure in contact with both the upper portion and the lower portion; and

a substrate positioned below said lower portion.

11. The multi-gate transistor of claim 10 wherein said gate structure further comprises a third portion positioned over said upper portion.

12. The multi-gate transistor of claim 10 wherein the first and second band gap creates a band gap offset between the valence bands of the upper and lower portions which is at least 0.4 electron volts.

13. The multi-gate transistor of claim 10 wherein said lower portion is formed from said substrate.

14. The multi-gate transistor of claim 10 further comprising an insulator between said lower portion and said substrate.

16. The multi-gate transistor of claim 10 wherein said first band gap is at least 0.4 electron volts narrower than said upper portion.

17. The multi-gate transistor of claim 11 wherein said upper portion has a thickness of approximately 450 Å

while the lower portion has a thickness of approximately 50 Å

.

18. The multi-gate transistor of claim 16 wherein said upper portion is formed from silicon-germanium.

19. The multi-gate transistor of claim 18 wherein said upper portion contains approximately 50 atomic percent of germanium.

20. The multi-gate transistor of claim 19 wherein said substrate is silicon.

15. The multi-gate transistor of 10 further comprising a gate insulator positioned between said gate structure and said fin.