SUBSTRATE BAND GAP ENGINEERED MULTI-GATE PMOS DEVICES
First Claim
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1. A multi-gate transistor comprising:
- a fin having an upper portion and a lower portion, said upper portion having a first band gap and said lower portion having a second band gap, larger than said first band gap to inhibit current flow from said upper portion to said lower portion;
a gate structure electrically coupled with said upper portion and said lower portion, the gate structure including a gate dielectric in direct contact with a sidewall of the upper and lower portions of the fin;
a source and drain region in the fin, wherein the source and drain regions are fully contained within the upper portion of the fin; and
a substrate positioned below said fin.
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Abstract
A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.
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Citations
20 Claims
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1. A multi-gate transistor comprising:
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a fin having an upper portion and a lower portion, said upper portion having a first band gap and said lower portion having a second band gap, larger than said first band gap to inhibit current flow from said upper portion to said lower portion; a gate structure electrically coupled with said upper portion and said lower portion, the gate structure including a gate dielectric in direct contact with a sidewall of the upper and lower portions of the fin; a source and drain region in the fin, wherein the source and drain regions are fully contained within the upper portion of the fin; and a substrate positioned below said fin. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A multi-gate transistor comprising:
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an upper portion having a first band gap, said upper portion fully containing a source region and a drain region of the transistor; a lower portion having a second band gap wider than said first band gap and positioned below said upper portion to form a fin; a gate structure having a first portion and a second portion, said first portion and second portion positioned on opposing sides of said fin and disposed over an undoped channel of said transistor, the gate structure in contact with both the upper portion and the lower portion; and a substrate positioned below said lower portion. - View Dependent Claims (11, 12, 13, 14, 16, 17, 18, 19, 20)
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15. The multi-gate transistor of 10 further comprising a gate insulator positioned between said gate structure and said fin.
Specification