INTEGRATED CIRCUIT INDUCTOR WITH DOPED SUBSTRATE

• US 20100193904A1
• Filed: 01/30/2009
• Published: 08/05/2010
• Est. Priority Date: 01/30/2009
• Status: Abandoned Application

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Watt, Jeffrey T., Chen, Shuxian
• Application Number:
  US12/363,545
• Publication Number:
  US 20100193904A1
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit inductor and a substrate with doped regions are provided. The substrate may be a p-type substrate and the substrate may have n-type doped regions. The n-type doped regions may include n-type wells, deep n-type wells, and n+ regions. The n-type doped regions may be formed in a pattern of strips such as a triangular comb pattern of strips or a series of L-shaped strips. The strips may be oriented perpendicular to the spiral of the inductor. A positive bias voltage may be applied to the n-type doped regions to create a depleted region in the substrate between the n-type doped regions. The depleted region may increase the effective distance between the inductor and the substrate, minimizing undesired coupling effects between the inductor and the substrate and increasing the effectiveness of the inductor.

Claims

1. An integrated circuit, comprising:

a spiral inductor; and

a p-type substrate that has n-type doped regions, wherein the n-type doped regions are arranged in a triangular comb-shaped pattern of strips on the p-type substrate, wherein the strips are perpendicular to the spiral of the inductor, and wherein the n-type doped regions are positively biased such that the p-type substrate is depleted between the strips of n-type doped regions.

2. The integrated circuit defined in claim 1, wherein the strips of n-type doped regions comprise strips of n-type wells.

3. The integrated circuit defined in claim 2, wherein the strips of n-type doped regions comprise n+ strips.

4. The integrated circuit defined in claim 3, wherein the n+ strips are silicided.

5. The integrated circuit defined in claim 1, wherein the strips of n-type doped regions comprise n+ strips formed in strips of n-type wells.

6. The integrated circuit defined in claim 5, wherein the n+ strips are silicided.

7. The integrated circuit defined in claim 1, wherein the strips of n-type doped regions comprise n-type wells formed over deep n-type wells.

8. The integrated circuit defined in claim 1, wherein the strips of n-type doped regions comprise n+ strips that are formed in strips of n-type wells and wherein the n-type wells are formed over deep n-type wells.

9. The integrated circuit defined in claim 8, wherein the n+ strips are silicided.

10. An integrated circuit, comprising:

a spiral inductor; and

a p-type substrate below the spiral inductor that has n-type doped regions, wherein the n-type doped regions are arranged in L-shaped strips on the p-type substrate.

11. The integrated circuit defined in claim 10, wherein the n-type doped regions are positively biased such that the p-type substrate is depleted between the L-shaped strips of n-type doped regions.

12. The integrated circuit defined in claim 11, wherein the strips of n-type doped regions comprise n+ strips.

13. The integrated circuit defined in claim 12, wherein the n+ strips are silicided.

14. The integrated circuit defined in claim 11, wherein the strips of n-type doped regions comprise n+ strips formed in strips of n-type wells.

15. The integrated circuit defined in claim 14, wherein the n+ strips are silicided.

16. The integrated circuit defined in claim 11, wherein the strips of n-type doped regions comprise n-type wells formed over deep n-type wells.

17. The integrated circuit defined in claim 11, wherein the strips of n-type doped regions comprise n+ strips that are formed in strips of n-type wells, wherein the n-type wells are formed over deep n-type wells.

18. The integrated circuit defined in claim 17, wherein the n+ strips are silicided.

19. An integrated circuit, comprising:

a spiral inductor; and

a p-type substrate below the spiral inductor that has n-type doped regions, wherein the n-type doped regions are positively biased such that the p-type substrate is completely depleted between the n-type doped regions.

20. The integrated circuit defined in claim 19, wherein the n-type doped regions comprise n-type wells.

21. The integrated circuit defined in claim 19, wherein the n-type doped regions comprise deep n-type wells.

22. The integrated circuit defined in claim 21, wherein the n-type doped regions comprise n+ regions.