MULTI-CHIP SEMICONDUCTOR DEVICES HAVING CONDUCTIVE VIAS AND METHODS OF FORMING THE SAME
First Claim
Patent Images
1. A multi-chip device comprising:
- a signal line having via contacts;
a plurality of chips in a stair-step arrangement formed on the signal line and having respective chip pads thereon;
a mold packaging material encapsulating the plurality of chips; and
at least one conductive via formed through the mold packaging material and electrically connecting one of the chip pads to one of the via contacts.
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Abstract
A multi-chip device can have a plurality of chips in a stair-step arrangement having respective chip pads thereon. A mold packaging material encapsulates the plurality of chips and at least one conductive via, that is in the mold packaging material and extends from an outer surface of the material, contacts a respective one of the chip pads. A conductive material is in the at least one conductive via.
112 Citations
20 Claims
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1. A multi-chip device comprising:
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a signal line having via contacts; a plurality of chips in a stair-step arrangement formed on the signal line and having respective chip pads thereon; a mold packaging material encapsulating the plurality of chips; and at least one conductive via formed through the mold packaging material and electrically connecting one of the chip pads to one of the via contacts. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A multi-chip device comprising:
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a plurality of first solder balls; a first signal line electrically connected to the plurality of first solder balls; a plurality of first chips in a first stair-step arrangement having respective chip pads thereon; a first mold packaging material encapsulates at least a portion of the plurality of first chips; a plurality of first conductive vias, in the first mold packaging material extending from a surface adjacent the first signal line to respective chip pads; a second signal line on the first mold packaging material opposite the first signal redistribution layer; a plurality of second solder balls on the second signal line wherein one of the second solder balls is electrically connected to the second signal line; a third signal line electrically connected to the plurality of second solder balls; a plurality of second chips in a second stair-step arrangement having respective chip pads thereon; a second mold packaging material encapsulates at least a portion of the plurality of second chips; and at least one second conductive via in the second mold packaging material extending from the third signal line to a respective one of the chip pads.
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Specification