Package-on-Package Using Through-Hole Via Die on Saw Streets

• US 20100193931A1
• Filed: 04/09/2010
• Published: 08/05/2010
• Est. Priority Date: 05/04/2007
• Status: Active Grant

• Current Assignee: Stats Chippac Limited
• Original Assignee: Stats Chippac Limited
• Inventors: Do, Byung Tai, Kuan, Heap Hoe, Chow, Seng Guan
• Granted Patent: US 9,847,253 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48472 : the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package.

Claims

1. A semiconductor device, comprising:

a first semiconductor die having a plurality of first contact pads formed on a surface of the first semiconductor die;

a first organic material deposited around a peripheral region of the first semiconductor die;

a plurality of first conductive through-hole vias (THV) formed through the first organic material in the peripheral region around the first semiconductor die;

a plurality of conductive traces formed over the surface of the first semiconductor die respectively between the first conductive THVs and first contact pads;

a plurality of first bumps formed over the first conductive THVs or the surface of the first semiconductor die;

a first encapsulant deposited over the first bumps, first semiconductor die, and first organic material, the first bumps being exposed from the first encapsulant; and

a second semiconductor die mounted over the first encapsulant and electrically connected to the first bumps.

2. The semiconductor device of claim 1, further including a plurality of bond wires connected between second contact pads formed on a surface of the first semiconductor die and second conductive THVs formed through the first organic material in the peripheral region around the first semiconductor die.

3. The semiconductor device of claim 1, wherein the second semiconductor die includes:

a second organic material deposited around a peripheral region of the second semiconductor die; and

a plurality of second conductive THV formed through the second organic material in the peripheral region around the second semiconductor die, the second conductive THVs being connected to the first bumps.

4. The semiconductor device of claim 3, wherein the second semiconductor die further includes:

a plurality of second bumps formed over the second conductive THVs or a surface of the second semiconductor die; and

a second encapsulant deposited over the second bumps, second semiconductor die, and second organic material, the second bumps being exposed from the second encapsulant.

5. The semiconductor device of claim 1, further including a third semiconductor die mounted to the surface of the first semiconductor die.

6. The semiconductor device of claim 1, wherein a portion of the first encapsulant is removed to expose the first semiconductor die and further including a third semiconductor die is mounted to the exposed first semiconductor die.

7. A semiconductor device, comprising:

a first semiconductor die;

a first organic material deposited around a peripheral region of the first semiconductor die;

first conductive vias formed through the first organic material in the peripheral region around the first semiconductor die;

a first interconnect structure formed over the first conductive vias or a surface of the first semiconductor die;

a first encapsulant deposited over the first interconnect structure, first semiconductor die, and first organic material, the first interconnect structure being exposed from the first encapsulant; and

a second semiconductor die mounted over the first encapsulant and electrically connected to the first interconnect structure.

8. The semiconductor device of claim 7, further including:

a contact pad formed on a surface of the first semiconductor die; and

a conductive trace formed over the surface of the first semiconductor die between the contact pad and one of the first conductive vias.

9. The semiconductor device of claim 7, wherein the second semiconductor die includes:

a second organic material deposited around a peripheral region of the second semiconductor die; and

second conductive vias formed through the second organic material in the peripheral region around the second semiconductor die, the second conductive vias being connected to the first interconnect structure.

10. The semiconductor device of claim 9, wherein the second semiconductor die further includes:

a second interconnect structure formed over the second conductive vias or a surface of the second semiconductor die; and

a second encapsulant deposited over the second interconnect structure, second semiconductor die, and second organic material, the second interconnect structure being exposed from the second encapsulant.

11. The semiconductor device of claim 7, further including a third semiconductor die mounted to the first semiconductor die.

12. The semiconductor device of claim 7, wherein a portion of the first encapsulant is removed to expose the first semiconductor die and further including a third semiconductor die is mounted to the exposed first semiconductor die.

13. The semiconductor device of claim 7, wherein the first interconnect structure includes a plurality of bumps.

14. A semiconductor device, comprising:

a first semiconductor die;

a first organic material deposited around a peripheral region of the first semiconductor die;

first conductive vias formed through the first organic material in the peripheral region around the first semiconductor die;

a first interconnect structure formed over the first conductive vias or a surface of the first semiconductor die; and

a second semiconductor die mounted over the first semiconductor die and electrically connected to the first interconnect structure.

15. The semiconductor device of claim 14, further including an encapsulant deposited over the first interconnect structure, first semiconductor die, and first organic material, the first interconnect structure being exposed from the encapsulant.

16. The semiconductor device of claim 15, wherein a portion of the first encapsulant is removed to expose the first semiconductor die and further including a third semiconductor die is mounted to the exposed first semiconductor die.

17. The semiconductor device of claim 14, further including:

a contact pad formed on a surface of the first semiconductor die; and

a conductive trace formed over the surface of the first semiconductor die between the contact pad and one of the first conductive vias.

18. The semiconductor device of claim 14, wherein the second semiconductor die includes:

a second organic material deposited around a peripheral region of the second semiconductor die; and

second conductive vias formed through the second organic material in the peripheral region around the second semiconductor die, the second conductive vias being connected to the first interconnect structure.

19. The semiconductor device of claim 18, wherein the second semiconductor die further includes:

a second interconnect structure formed over the second conductive vias or a surface of the second semiconductor die; and

an encapsulant deposited over the second interconnect structure, second semiconductor die, and second organic material, the second interconnect structure being exposed from the second encapsulant.

20. The semiconductor device of claim 14, wherein the first interconnect structure includes a plurality of bumps.

21. A semiconductor device, comprising a plurality of stacked semiconductor die each including:

an organic material deposited around a peripheral region of the semiconductor die;

a plurality of conductive vias formed through the organic material in a peripheral region around the semiconductor die; and

an interconnect structure formed over the conductive vias or a surface of the semiconductor die.

22. The semiconductor device of claim 21, further including an encapsulant deposited over the interconnect structure, semiconductor die, and organic material, the interconnect structure being exposed from the encapsulant.

23. The semiconductor device of claim 22, wherein a portion of the encapsulant is removed to expose the semiconductor die and further including a second semiconductor die is mounted to the exposed semiconductor die.

24. The semiconductor device of claim 21, further including:

a contact pad formed on a surface of the semiconductor die; and

a conductive trace formed over the surface of the semiconductor die between the contact pad and one of the conductive vias.

25. The semiconductor device of claim 21, wherein the interconnect structure includes a plurality of bumps.