METHOD OF MAKING 3D INTEGRATED CIRCUITS AND STRUCTURES FORMED THEREBY
First Claim
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1. A method of making 3D integrated circuits, comprising the steps of:
- (a) forming at least one trench in a first semiconductor wafer;
(b) filling the at least one trench with an insulator to form a filled trench;
(c) forming devices and back end of the line (BEOL) wiring on a first side of the first semiconductor wafer with at least one pad in the BEOL wiring aligned with the at least one filled trench;
(d) joining the first semiconductor wafer to a second semiconductor wafer having at least one landing pad aligned with the at least one filled trench in the first semiconductor wafer;
(e) etching the at least one filled trench to remove the insulator;
(f) forming an insulative spacer on the walls of the at least one trench;
(g) continuing etching the at least one trench until the at least one pad and the at least one landing pad are exposed; and
(h) filling the at least one trench with an electrical conductor.
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Abstract
A method and structure of connecting at least two integrated circuits in a 3D arrangement by a through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit.
283 Citations
18 Claims
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1. A method of making 3D integrated circuits, comprising the steps of:
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(a) forming at least one trench in a first semiconductor wafer; (b) filling the at least one trench with an insulator to form a filled trench; (c) forming devices and back end of the line (BEOL) wiring on a first side of the first semiconductor wafer with at least one pad in the BEOL wiring aligned with the at least one filled trench; (d) joining the first semiconductor wafer to a second semiconductor wafer having at least one landing pad aligned with the at least one filled trench in the first semiconductor wafer; (e) etching the at least one filled trench to remove the insulator; (f) forming an insulative spacer on the walls of the at least one trench; (g) continuing etching the at least one trench until the at least one pad and the at least one landing pad are exposed; and (h) filling the at least one trench with an electrical conductor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of making 3D integrated circuits, comprising the steps of:
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(a) forming at least one trench in a first semiconductor wafer, the at least one trench extending from a first side of the first semiconductor wafer; (b) filling the at least one trench with an insulator; (c) forming devices and back end of the line (BEOL) wiring on the first side of the first semiconductor wafer with at least one pad in the BEOL wiring aligned with the at least one trench, the BEOL wiring having an exposed surface; (d) obtaining a second semiconductor wafer having BEOL wiring, the BEOL wiring having at least one landing pad and an exposed surface; (e) joining the exposed surface of the BEOL wiring of the first semiconductor wafer to the exposed surface of the BEOL wiring of the second semiconductor wafer such that the at least one landing pad is aligned with the at least one trench; (f) etching the first semiconductor wafer from a second side so as to join with the at least one trench and continuing etching of the at least one trench to remove the insulator and stopping in the BEOL wiring; (g) forming an oxide spacer on the walls of the at least one trench; (h) continuing etching the at least one trench until the at least one pad and the at least one landing pad are exposed; and (i) filling the at least one trench with an electrical conductor. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A 3D integrated circuit comprising:
a first integrated circuit having a connection pad mechanically and electrically joined to a second integrated circuit having a connection pad and a single metal-filled via making simultaneous connection with the first integrated circuit connection pad and the second integrated circuit connection pad wherein the single via has a center portion, two ends and a width which is narrower in the center portion than at the two ends. - View Dependent Claims (16, 17, 18)
Specification