Current Control Circuits

• US 20100194462A1
• Filed: 02/02/2009
• Published: 08/05/2010
• Est. Priority Date: 02/02/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Ladurner, Markus, Petruzzi, Luca, Meldt, Bernhard, Croce, Paolo Del, Apostol, Adrian, Matei, Vasile
• Granted Patent: US 7,911,260 B2
• Time in Patent Office: Days
• US Class Current: 327/427
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0027 Measuring means of, e.g. currents through or voltages across the switch

Abstract

Circuit, system and method of current control circuits are disclosed. In one embodiment, a control circuit includes a first MOS transistor and a second MOS transistor. The first source/drains of the first and the second MOS transistors are coupled to an output of a power source. A second source/drain of the first MOS transistor is coupled to a first output node of the current control circuit. A second source/drain of the second MOS transistor is coupled to a second output node of the current control circuit. The control circuit further includes a means to block flow of current from the first output node of the current control circuit to the second output node of the current control circuit.

Claims

1. A current control circuit comprising:

a first MOS transistor having a first source/drain coupled to an output of a power source, and a second source/drain of the first MOS transistor coupled to a first output node of the current control circuit;

a second MOS transistor having a first source/drain coupled to the output of the power source, a second source/drain of the second MOS transistor coupled to a second output node of the current control circuit; and

means for blocking flow of current from the first output node of the current control circuit to the second output node of the current control circuit when a potential at the first output node is higher than a potential at the output of the power source.

2. The circuit of claim 1, wherein the means for blocking flow of current from the first output node of the current control circuit to the second output node of the current control circuit comprises a switch coupled between the output of the power source and the first output node of the current control circuit, wherein the switch is configured to conduct when the potential at the first output node is higher than the potential at the output of the power source.

3. The circuit of claim 2, further comprising a comparator, a first input of the comparator coupled to the output of the power source, a second input of the comparator coupled to the first output node of the current control circuit, wherein the comparator causes the switch to conduct when the potential at the first output node is higher than the potential of the output of the power source.

4. The circuit of claim 3, wherein the comparator comprises a voltage comparator, wherein the voltage comparator enables the switch to conduct if the potential at the first output node is higher than the potential of the output of the power source by a predetermined voltage.

5. The circuit of claim 4, wherein the predetermined voltage is about 50 mV.

6. The circuit of claim 2, wherein the means for blocking flow of current from the first output node of the current control circuit to the second output node of the current control circuit further comprises a blocking diode, wherein the second source/drain of the second MOS transistor is coupled to the second output node of the current control circuit through the blocking diode, and wherein the blocking diode is configured to block a flow of current when the potential at the first output node is higher than the potential at the output of the power source.

7. The circuit of claim 1, wherein the first output node is configured to couple to a load, and wherein the second output node is configured to couple to a sense resistor.

8. The circuit of claim 1, wherein gates of the first and the second MOS transistors are coupled together.

9. The circuit of claim 1, wherein the first MOS transistor comprises a power DMOS transistor, and wherein the second MOS transistor comprises a sense DMOS transistor.

10. The circuit of claim 9, wherein the sense DMOS transistor comprises an effective width that is smaller than the power DMOS transistor.

11. The circuit of claim 9, wherein an effective width of the sense DMOS transistor is at least 2000 times smaller than an effective width of the power DMOS transistor.

12. The circuit of claim 1, wherein the second source/drain of the first MOS transistor is coupled to the second source/drain of the second MOS transistor through a third MOS transistor.

13. The circuit of claim 12, wherein the third MOS transistor comprises a high voltage PMOS transistor, wherein a gate of the third MOS transistor is coupled to the second source/drain of the first MOS transistor.

14. The circuit of claim 12, further comprising:

an operational amplifier with a first input coupled to the first output node of the control circuit, a second input of the operational amplifier coupled to the second source/drain of the second MOS transistor; and

a fourth MOS transistor having a first source/drain coupled to the second source/drain of the second MOS transistor, wherein an output of the operational amplifier is coupled to a gate of the fourth MOS transistor.

15. The circuit of claim 14, wherein the first input of the operational amplifier is coupled to the first output node of the control circuit through a second blocking diode, and the second input of the operational amplifier is coupled to the second source/drain of the second MOS transistor through a third blocking diode.

16. The circuit of claim 1, wherein the means for blocking flow of current from the first output node of the current control circuit to the second output node of the current control circuit comprises a blocking diode, wherein the second source/drain of the second MOS transistor is coupled to an input of the blocking diode, wherein an output of the blocking diode is coupled to the second output node of the control circuit, wherein the blocking diode is reverse biased when the potential at the first output node is higher than the potential at the output of the power source.

17. The circuit of claim 16, wherein the blocking diode does not block a flow of current if a potential at the first output node is not higher than a potential at the output of the power source.

18. The circuit of claim 16, wherein the blocking diode comprises a PMOS transistor, wherein a first source/drain of the PMOS transistor is coupled to the second source/drain of the second MOS transistor, wherein a bulk contact of the PMOS transistor is shorted to the first source/drain of the PMOS transistor, and wherein a second source/drain of the PMOS transistor is coupled to the second output of the control circuit.

19. The circuit of claim 18, wherein the first source/drain of the PMOS transistor is coupled to the second source/drain of the second MOS transistor through a third MOS transistor.

20. The circuit of claim 16, wherein the blocking diode comprises a NMOS transistor, wherein a first source/drain of the NMOS transistor is coupled to the second source/drain of the second MOS transistor, wherein a second source/drain of the NMOS transistor is coupled to the second output of the control circuit, and wherein a bulk contact of the NMOS transistor is shorted to the second source/drain of the NMOS transistor.

21. The circuit of claim 20, wherein the first source/drain of the NMOS transistor is coupled to the second source/drain of the second MOS transistor through a third MOS transistor.

22. A method of operating a control circuit from inverse current, the method comprising:

providing a control circuit comprising a power transistor and a sense transistor, wherein a first source/drain of the power transistor is coupled to an output node of a power source, wherein a second source/drain of the power transistor is coupled to an first output node of the control circuit, the first output node being configured to be coupled to a load, wherein a first source/drain of the sense transistor is coupled to the output of the power source, wherein a second source/drain of the second MOS transistor is coupled to a second output of the control circuit, and wherein the second output of the control circuit is configured to be coupled to a sense resistor; and

blocking current flow from the first output node of the control circuit to the second output of the control circuit when a potential at the first output of the control circuit is larger than a potential at the output of the power source.

23. The method of claim 22, wherein blocking current flow from the first output node of the control circuit to the second output of the control circuit comprises:

comparing the potential at the first output of the control circuit with the potential at the output node of the power source;

generating a sense signal if the potential at the first output of the control circuit is larger than the potential at the output of the power source; and

coupling the first output and the first input using a switch, the switch being activated by the sense signal.

24. The method of claim 23, wherein the control circuit further comprises:

a comparator to compare the potential at the first output of the control circuit with the potential at the output node of the power source, wherein the comparator generates the sense signal;

an operational amplifier with a first input coupled to the first source/drain of the power transistor, a second input of the operational amplifier coupled to the second source/drain of the sense transistor;

a MOS transistor; and

a first source/drain of the MOS transistor coupled to the second source/drain of the sense transistor, wherein an output of the operational amplifier is coupled to a gate of the MOS transistor.

25. The method of claim 23, wherein blocking current flow from the first output node of the control circuit to the second output of the control circuit comprises:

activating a blocking diode if a potential at the power source is not greater than the potential at the first output node, the blocking diode being configured to block a flow of current if activated; and

deactivating the blocking diode if a potential at the power source is greater than the potential at the first output node, wherein a second source/drain of the second MOS transistor is coupled to an input of the blocking diode, wherein an output of the blocking diode is coupled to a second output of the control circuit through a MOS transistor, and wherein the second output of the control circuit is configured to be coupled to a sense resistor.

26. The method of claim 25, wherein the blocking diode comprises a PMOS transistor, wherein a first source/drain of the PMOS transistor is coupled to the second source/drain of the second MOS transistor, wherein a bulk contact of the PMOS transistor is shorted to the first source/drain of the PMOS transistor, wherein a second source/drain of the PMOS transistor is coupled to the second output of the control circuit, and wherein the control circuit further comprises:

a third MOS transistor, wherein the first source/drain of the PMOS transistor is coupled to the second source/drain of the second MOS transistor through a third MOS transistor;

a fourth MOS transistor, wherein the second source/drain of the first MOS transistor is coupled to the second source/drain of the second MOS transistor through the fourth MOS transistor;

an operational amplifier with a first input coupled to the first output node of the control circuit, a second input of the operational amplifier coupled to the second source/drain of the second MOS transistor; and

a fifth MOS transistor having a first source/drain, the first source/drain of the fifth MOS coupled to the second source/drain of the second MOS transistor through the blocking diode, wherein an output of the operational amplifier is coupled to a gate of the fifth MOS transistor.

27. A current control circuit comprising:

a first MOS transistor having a first source/drain coupled to an output of a power source, and a second source/drain coupled to a first output node of the current control circuit;

a second MOS transistor having a first source/drain coupled to the output of the power source, and a second source/drain coupled to a second output node of the current control circuit;

a comparator, a first input of the comparator coupled to the output of the power source, a second input of the comparator coupled to the first output node of the current control circuit; and

a switch coupled to an output of the comparator.

28. The circuit of claim 27, wherein the switch is coupled between the output of the power source and the first output node of the current control circuit.

29. A current control circuit comprising:

a first MOS transistor having a first source/drain coupled to an output of a power source, and a second source/drain coupled to a first output node of the current control circuit;

a second MOS transistor having a first source/drain coupled to the output of the power source, and a second source/drain coupled to a second output node of the current control circuit; and

a first blocking diode, wherein the second source/drain of the second MOS transistor is coupled to an input of the first blocking diode, wherein an output of the first blocking diode is coupled to a second output node of the control circuit.

30. The circuit of claim 29, further comprising:

a third MOS transistor, wherein the second source/drain of the first MOS transistor is coupled to the second source/drain of the second MOS transistor through the third MOS transistor, wherein a gate of the third MOS transistor is coupled to the second source/drain of the first MOS transistor;

an operational amplifier with a first input coupled to the first output node of the control circuit, a second input of the operational amplifier coupled to the second source/drain of the second MOS transistor;

a fourth MOS transistor having a first source/drain of the fourth MOS coupled to the second source/drain of the second MOS transistor, wherein an output of the operational amplifier is coupled to a gate of the fourth MOS transistor.

31. The circuit of claim 30, wherein the first input of the operational amplifier is coupled to the first output node of the control circuit through a second blocking diode, and the second input of the operational amplifier is coupled to the second source/drain of the second MOS transistor through a third blocking diode.