ACCURATE PERSISTENT NODES

• US 20100194543A1
• Filed: 04/14/2010
• Published: 08/05/2010
• Est. Priority Date: 05/06/2005
• Status: Active Grant

• Current Assignee: Zest Labs, Inc.
• Original Assignee: Intelleflex Corporation
• Inventors: Stewart, Roger Green
• Granted Patent: US 8,400,274 B2
• Time in Patent Office: Days
• US Class Current: 340/10.3
• CPC Class Codes: G05F 3/16 being semiconductor devices
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06M 3/02 for performing an operation at a predetermined value of the count, e.g. arresting a machine G06M3/04 takes precedence
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier

Abstract

A timing circuit that can function as an accurate persistent node in an RFID tag includes a power capture circuit for capturing power from a power source, and a counter circuit that provides a count representing a progression of time. The count can then be compared to a reference value representing a time constant of the circuit.

Claims

1. A calibrated gate biasing circuit, comprising:

a switched capacitor precision resistor; and

a voltage reference.

2. The circuit of claim 1, wherein the voltage reference includes a matrix of forward biased diodes coupled to an outlet of the switched capacitor precision resistor.

3. The circuit of claim 2, wherein the matrix is calibrated based on a reference frequency.

4. The circuit of claim 3, wherein the reference frequency is received from a remote device.

5. The circuit of claim 1, wherein the current being controlled is less than about 10 picoamperes (pA).

6. The circuit of claim 1, wherein the circuit is embodied on a Radio Frequency Identification (RFID) tag.

7. An electronic circuit for initiating a change in state of a host device, comprising:

a counter coupled to a host device, the counter counting at a fixed interval,

wherein the counter is reset to zero upon receiving a command from a remote device,

wherein the count is compared to a reference value,

wherein the host device changes states if the count matches the reference value,

wherein operation of the counter continues in spite of an interruption in power supply from a power source.

8. The circuit of claim 7, wherein the circuit is embodied on a Radio Frequency Identification (RFID) tag.

12. An RFID system, comprising:

an RFID tag implementing the circuit of claim 7; and

an RFID reader in communication with the RFID tag.

9. A method for counting Radio Frequency Identification (RFID) tags, comprising:

interrogating each RFID tag in range of a reader;

receiving a tag identifier from each RFID tag;

instructing each tag to sleep upon receiving the tag identifier from the tag,

wherein each tag remains in the sleep state for a known period of time,

wherein the known period of time does not significantly vary regardless of whether the tag is powered or not, and

generating a count of the tags.

10. The method of claim 9, wherein each tag is interrogated only once prior to generating the count.

11. An RFID system, comprising:

an RFID tag implementing the circuit of claim I; and

an RFID reader in communication with the RFID tag.

13. A method for counting Radio Frequency Identification (RFID) tags, comprising:

interrogating each RFID tag in range of a reader;

receiving a tag identifier from each RFID tag;

instructing each tag to sleep upon receiving the tag identifier from the tag,

wherein each tag automatically returns to a wake state after a time interval has elapsed,

wherein the time interval is bounded between a minimum and a maximum value; and

generating a count of the tags.

14. The method of claim 13, wherein the time interval does not significantly vary regardless of whether the tag is powered or not.

15. The method of claim 13, wherein the maximum ratio of maximum value to minimum value is less than 10:

1.

16. An asymmetrical differential amplifier, comprising:

a first transistor having a channel length of length A and a channel width of width B;

a second transistor having a different geometry than the first transistor such that the second transistor has a different threshold voltage than the first transistor,

wherein the amount of bias is greater than the mismatch of the threshold voltages of the transistors of the differential amplifier.

17. The differential amplifier of claim 16, wherein the channel length of the second transistor is different than the channel length of the first transistor.

18. The differential amplifier of claim 16, wherein the channel width of the second transistor is different than the channel width of the first transistor.

19. An asymmetrical differential amplifier, wherein the differential amplifier has a first output when a source voltage is greater than a voltage on a node, wherein the differential amplifier has a second output when the source voltage is less than or equal to the voltage on the node.