CAPACITOR STRUCTURE HAVING IMPROVED AREA EFFICIENCY, A MEMORY DEVICE INCLUDING THE SAME, AND A METHOD OF FORMING THE SAME

• US 20100195392A1
• Filed: 02/03/2009
• Published: 08/05/2010
• Est. Priority Date: 02/03/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Freeman, Eric H.
• Granted Patent: US 8,680,650 B2
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 28/88 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed.

Claims

1. A capacitor structure, comprising:

a plurality of conductive structures overlying a semiconductor substrate and laterally spaced from one another by a gap;

a dielectric material filling the gap between each of the plurality of conductive structures, wherein a thickness of the dielectric material between adjacent conductive structures of the plurality of conductive is selected based on a dielectric constant of the dielectric material and a maximum voltage to be applied to the conductive structures.

2. The capacitor structure of claim 1, wherein each of the plurality of conductive structures is laterally spaced from one another by less than about 65 nm.

3. The capacitor structure of claim 1, wherein at least one of the plurality of conductive structures has a width of less than about 65 nm.

4. The capacitor structure of claim 1, wherein each of the plurality of conductive structures is disposed on an intermediate material overlying and contacting the semiconductor substrate.

5. The capacitor structure of claim 1, wherein each of the plurality of conductive structures are substantially parallel with one another.

6. The capacitor structure of claim 1, wherein the thickness of the dielectric material is selected to withstand a voltage of between about 10 volts and about 60 volts.

7. The capacitor structure of claim 1, wherein each of the plurality of conductive structures has a height of from about 50 nm to about 180 nm.

8. The capacitor structure of claim 1, wherein each of the plurality of conductive structures is laterally spaced from an adjacent conductive structure by a distance of between about 15 nm and about 100 nm.

9. The capacitor structure of claim 1, wherein the plurality of conductive structures are equilaterally spaced from one another.

10. The capacitor structure of claim 1, further comprising an oxide-nitride-oxide material overlying the plurality of conductive structures.

11. A memory device comprising:

a memory array comprising a plurality of memory cells arranged in rows and columns, each row coupled to a word line and each column coupled to a bit line;

a charge pump circuit coupled to the memory array for generating a applied voltage; and

a capacitor structure coupled to the charge pump circuit for controlling operation of the charge pump circuit, the capacitor comprising a plurality of conductive structures spaced apart from one another by a thickness of a dielectric material selected based on a dielectric constant thereof and a applied voltage to be generated by the charge pump circuit.

12. The memory device of claim 11, wherein the memory device is a fully formed NAND memory device.

13. The memory device of claim 11, wherein each of the plurality of conductive structures comprises an elongate portion and another portion extending perpendicular to the elongate portion.

14. The memory device of claim 11, wherein the applied voltage comprises about 20 volts.

15. The memory device of claim 11, wherein the thickness of the dielectric material is based on the dielectric constant of the dielectric material and a predetermined voltage.

16. A method of forming a capacitor structure, comprising:

forming a plurality of conductive structures, each of the plurality of conductive structures laterally spaced from one another a distance equal to a desired thickness of a dielectric material disposed therebetween; and

determining the desired thickness of the dielectric material based on a dielectric constant thereof and a voltage to be applied to the plurality of conductive structures.

17. The method of claim 16, wherein forming the plurality of conductive structures comprises:

forming a plurality of discrete regions of a sacrificial material on a conductive material;

applying a spacer material over the plurality of discrete regions and exposed surfaces of the conductive material;

removing a portion of the spacer material to form a plurality of spacers laterally adjacent sidewalls of each of the plurality of discrete regions;

removing the plurality of discrete regions to expose a surface of the conductive material between the plurality of spacers; and

removing a portion of the conductive material exposed through the plurality of spacers to form the plurality of conductive structures overlying an intermediate material.

18. The method of claim 17, wherein removing the plurality of discrete regions to expose a surface of the conductive material between the plurality of spacers comprises forming gaps having a width of from about 20 nm to about 30 nm between the plurality of spacers.

19. The method of claim 17, wherein removing a portion of the spacer material to form a plurality of spacers comprises forming a plurality of spacers spaced apart from one another by less than about 65 nm.

20. The method of claim 16, wherein forming a plurality of conductive structures, each of the plurality of conductive structures laterally spaced from one another a distance equal to a desired thickness of a dielectric material disposed therebetween comprises varying the distance between each of the conductive structures according to a dielectric constant of the dielectric material.

21. The method of claim 16, wherein determining the desired thickness of the dielectric material based on a dielectric constant thereof and a voltage to be applied to the plurality of conductive structures comprises determining a desired thickness of the dielectric material based on a dielectric constant thereof and a applied voltage of a NAND memory device.