Apparatus and method for timing synchronization in a communication system

• US 20100195565A1
• Filed: 02/01/2010
• Published: 08/05/2010
• Est. Priority Date: 02/02/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shin, Seung-Woo, Kim, Ki-Hyun
• Granted Patent: US 8,472,370 B2
• Time in Patent Office: Days
• US Class Current: 370/326
• CPC Class Codes: H04J 3/0644 External master-clock
• CPC Class Codes: H04J 3/0682 by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
• CPC Class Codes: H04L 43/0852 Delays

Abstract

An apparatus is capable of restoring a clock of a second node in a communication system with a symmetric network construction of a first node that is capable of receiving a Global Positioning System (GPS) signal, and the second node that is not capable of receiving a GPS signal. The method includes identifying synchronization information received from the first node, determining a delay with the first node, generating a clock using the synchronization information and delay, removing a clock phase being out of a reference range in a phase identification interval, dividing the phase identification interval into at least two subdivision intervals, and removing a clock phase being out of a normal operation range of a phase in each subdivision interval.

Claims

1. A method for restoring a clock of a second node in a communication system with a symmetric network construction of a first node capable of receiving a Global Positioning System (GPS) signal, the second node not capable of receiving the GPS signal, the method comprising:

identifying synchronization information received from the first node;

determining a delay with the first node;

generating the clock using the synchronization information and the delay;

removing a clock phase that is out of a reference range in a phase identification interval;

dividing the phase identification interval into at least two subdivision intervals; and

removing a clock phase value that is out of a predetermined normal operation range of a phase in each subdivision interval.

2. The method of claim 1, wherein identifying the synchronization information comprises identifying synchronization information comprised in packets received from the first node through a wired network.

3. The method of claim 1, wherein determining the delay comprises:

transmitting a delay request message to the first node;

in response to receiving a delay response message from the first node, identifying, in the delay response message, a request receive time at which the first node receives the delay request message and a response transmit time at which the first node transmits the delay response message; and

determining the delay with the first node using a request transmit time at which the delay request message was transmitted, a response receive time at which the delay response message was received, the request receive time, and the response transmit time.

4. The method of claim 1, wherein removing the clock phase that is out of the reference range comprises:

determining the clock phase comprised in the phase identification interval; and

removing the clock phase that is out of the reference range in the phase identification interval.

5. The method of claim 1, wherein removing the clock phase that is out of the reference range comprises:

determining the clock phase comprised in the phase identification interval; and

replacing the clock phase that is out of the reference range in the phase identification interval with an average clock phase value.

6. The method of claim 1, wherein the reference range is set to have a predetermined error range based on an average of clock phases of a predetermined period of time.

7. The method of claim 1, wherein removing the clock phase that is out of the predetermined normal operation range comprises:

selecting the minimum clock phase value from each subdivision interval; and

removing the minimum clock phase value that is out of the predetermined normal operation range for each subdivision interval.

8. The method of claim 7, wherein removing the clock phase that is out of the predetermined normal operation range comprises:

determining, for each subdivision interval, whether the minimum clock phase value is included in a table comprising phase information for a normal operation of the second node; and

discarding the minimum clock phase value that is not included in the table.

9. The method of claim 8, wherein the table comprises clock phase information arranged by normal operation temperatures of the second node.

10. The method of claim 7, wherein removing the clock phase that is out of the predetermined normal operation range comprises:

determining, for each subdivision interval, whether the minimum clock phase value is included in a table comprising phase information for a normal operation of the second node; and

replacing the minimum clock phase value that is not included in the table with an average minimum clock phase value.

11. The method of claim 10, wherein the average minimum clock phase value is continuously calculated through a vector component.

12. The method of claim 1, further comprising, outputting a clock when the minimum clock phase value is within the predetermined normal operation range.

13. An apparatus for restoring a clock of a second node in a communication system with a symmetric network construction of a first node capable of receiving a Global Positioning System (GPS) signal, the second node not capable of receiving a GPS signal, the apparatus comprising:

an interface configured to communicate with the first node;

a delay determiner configured to determine a delay with the first node;

a clock generator configured to generate the clock using synchronization information received from the first node through the interface and the delay determined in the delay determiner; and

a clock corrector configured to remove a clock phase that is out of a reference range in a phase identification interval among clocks generated in the clock generator, and removing a clock phase value that is out of a predetermined normal operation range in each of at least two subdivision intervals of the phase identification interval.

14. The apparatus of claim 13, wherein the clock generator generates the clock using the synchronization information comprised in packets received from the first node through a wired network and the delay determined in the delay determiner.

15. The apparatus of claim 13, wherein, the delay determiner is further configured to transmit a delay request message to the first node through the interface and receive a delay response message from the first node through the interface, wherein the delay determiner determines the delay with the first node based on a request transmit time for transmitting the delay request message, a response receive time for receiving the delay response message, a request receive time at which the first node receives the delay request message, and a request transmit time at which the first node transmits the delay response message, which are determined in the delay response message.

16. The apparatus of claim 13, wherein the clock corrector comprises a phase filter configured to remove the clock phase that is out of a reference range in the phase identification interval.

17. The apparatus of claim 13, wherein the clock corrector comprises a phase filter for replacing the clock phase that is out of a reference range in the phase identification interval with an average clock phase value.

18. The apparatus of claim 13, wherein the clock corrector determines whether to remove the clock phase, using a reference range that is set to have a predetermined error range on the basis of an average of clock phases of a predetermined period of time.

19. The apparatus of claim 13, wherein the clock corrector comprises:

a phase filter configured to remove the clock phase that is out of a reference range in the phase identification interval;

a set constructor configured to divide the phase identification interval into at least two subdivision intervals;

a minimum value selector configured to select the minimum clock phase value of each subdivision interval; and

an output controller configured to output the clock from which the clock phase that is out of the predetermined normal operation range is removed from each subdivision interval.

20. The apparatus of claim 13, wherein the clock corrector selects the minimum clock phase value of each subdivision interval, and removes the minimum clock phase value that is out of a normal operation range for each subdivision interval.

21. The apparatus of claim 20, wherein the clock corrector is further configured to determine whether the minimum clock phase value of each subdivision interval is included in a table comprising phase information enabling a normal operation of the second node and discard the minimum clock phase value that is not found in the table.

22. The apparatus of claim 21, wherein the table comprises clock phase information arranged by normal operation temperatures of the second node.

23. The apparatus of claim 20, wherein the clock corrector is further configured to replace the minimum clock phase value with an average minimum clock phase value when the minimum clock phase value is not found in the table.

24. The apparatus of claim 23, wherein the table comprises clock phase information arranged by normal operation temperatures of the second node.