BIT ALOCATION AMONG CARRIERS IN MULTICARRIER COMMUNICATIONS

• US 20100195755A1
• Filed: 04/15/2010
• Published: 08/05/2010
• Est. Priority Date: 11/25/1998
• Status: Active Grant

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Daphimo Co BV LLC (Intellectual Ventures LLC)
• Inventors: Tzannes, Marcos C., Sandberg, Stuart D., Shapiro, Jerome M.
• Granted Patent: US 8,218,664 B2
• Time in Patent Office: Days
• US Class Current: 375/285
• CPC Class Codes: H04L 1/004 by using forward error control H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00
• CPC Class Codes: H04L 5/0044 allocation of payload

Abstract

A technique is provided that may be employed in multicarrier communications to improve the efficiency of error correction using symbol-oriented error correction methodologies, by reducing the number of error correction code symbols (102, 104 . . . ) that are received in error that result from a single channel error. More specifically, in this technique, bits from the symbols are allocated among the channels in such a way as to minimize the number of respective channels that are allocated bits belonging to more that one respective symbol during a respective transmission period.

Claims

1-38. -38. (canceled)

39. A multicarrier data modulation method, comprising:

using a plurality of carrier signals, by a transmitter, to modulate a plurality of data bit signals of a serial input data stream, wherein subsets of the plurality of data bit signals comprise error correction symbols, and wherein a number of data bit signals modulable on at least one carrier signal is fewer than a bit size of one of the error correction symbols; and

allocating, by the transmitter, the plurality of data bit signals among the plurality of carrier signals, wherein said allocating includes accounting for a number of carrier signals that modulate data bit signals belonging to different error correction symbols during a transmission period.

40. The multicarrier data modulation method of claim 39, wherein said allocating of the plurality of data bit signals includes adjusting a signal-to-noise margin of at least one channel.

41. The multicarrier data modulation method of claim 40, wherein a signal-to-noise ratio (SNR) of the at least one channel is approximately or exactly equal to a sum of the SNR margin and a minimum required SNR for the at least one channel, wherein data bit signals to be transmitted via the at least one channel belong to more than one error correction symbol during the transmission period, and wherein said adjusting comprises increasing the SNR margin so as to reduce a number of data bit signals transmittable by the at least one channel at a predetermined bit error rate probability.

42. The multicarrier data modulation method of claim 40, wherein said adjusting comprises assigning, to the at least one channel, data bit signals from only a single error correction symbol during a transmission period.

43. The multicarrier data modulation method of claim 39, wherein said allocating comprises reducing the number of carrier signals that modulate data bits signals belonging to different error correction symbols.

44. The multicarrier data modulation method of claim 39, wherein said allocating comprises minimizing the number of carrier signals that modulate data bits signals belonging to different error correction symbols.

45. A method for modulating data bit signals over a transmission channel having a plurality of subchannels, comprising:

including, by a transmitter, a predetermined number of data bit signals of an input data stream in each of a plurality of error correction symbols; and

allocating, by the transmitter, a plurality of data bit signals among groups of the plurality of subchannels such that a number of subchannels that modulate data bit signals from more than one error correction symbol during a transmission period is reduced or minimized.

46. The method of claim 45, further comprising modulating, by the transmitter, the plurality of data bit signals over the plurality of subchannels, including modulating fewer than the predetermined number of data bit signals over at least one of the plurality of subchannels.

47. The method of claim 45, further comprising grouping, by the transmitter, the plurality of subchannels into groups comprised of one or more subchannels based on a number of data bit signals modulable over the subchannels.

48. The method of claim 47, further comprising adjusting, by the transmitter, a number of data bit signals modulable over a given subchannel including adjusting a signal-to-noise ratio for the given subchannel.

49. The method of claim 45, wherein said allocating further comprises determining a subchannel order in which to allocate the plurality of data bit signals of the plurality of error correction symbols to the subchannels.

50. The method of claim 49, wherein the subchannel order is based upon at least a bit size of the plurality of error correction symbols and numbers of data bit signals modulable over each of the plurality of subchannels.

51. The method of claim 45, further comprising adjusting, by the transmitter, a number of data bit signals modulable over a given subchannel to reduce or minimize the number of subchannels that modulate data bit signals from more than one error correction symbol during a transmission period.

52. The method of claim 51, wherein said adjusting a number of data bit signals modulable over a given subchannel comprises adjusting a transmission gain for the given subchannel.

53. The method of claim 45, wherein said allocating occurs during initialization of a multicarrier transceiver.

54. A multicarrier modulation system, comprising:

a transceiver configured to generate a plurality of carrier signals for use in modulating a plurality of data bit signals of a serial input data stream; and

a processor coupled to the transceiver and configured to;

cause the transceiver to transmit the plurality of data bit signals over a plurality of carrier signals, wherein subsets of the plurality of data bit signals comprise error correction symbols, and wherein a number of data bit signals modulable on at least one carrier signal is fewer than a bit size of a one of the error correction symbols; and

allocate the plurality of data bit signals among the plurality of carrier signals, such that a number of carrier signals that are to modulate data bit signals belonging to different error correction symbols during a transmission period is accounted for.

55. The multicarrier modulation system of claim 54, wherein the processor is further configured to allocate the plurality of data bit signals based on an adjustment of a signal-to-noise margin of at least one channel.

56. The multicarrier modulation system of claim 55, wherein a signal-to-noise ratio (SNR) of the at the least one channel is approximately or exactly equal to a sum of the SNR margin and a minimum required SNR for the at least one channel, wherein data bit signals to be transmitted via the at least one channel belong to more than one error correction symbol during the transmission period, and wherein the processor is further configured to perform the adjustment by an increase in the SNR margin so as to reduce a number of data bit signals transmittable by the at least one channel at a predetermined bit error rate probability.

57. The multicarrier modulation system of claim 55, wherein the processor is further configured to perform the adjustment by an assignment, to the at least one channel, of data bit signals from only a single error correction symbol for a transmission period.

58. The multicarrier modulation system of claim 54, wherein the processor is configured to reduce the number of carrier signals that are to modulate data bits signals belonging to different error correction symbols.

59. The multicarrier modulation system of claim 54, wherein the processor is further configured to minimize the number of carrier signals that modulate data bits signals belonging to different error correction symbols during a transmission period.

60. A multicarrier modulation system, comprising:

a transceiver configured to generate a plurality of carrier signals for use in modulating a plurality of data bit signals of a serial input data stream; and

a processor coupled to the transceiver and configured to;

include a predetermined number of data bit signals of the serial input data stream in each of a plurality of error correction symbols; and

allocate the plurality of data bit signals among groups of subchannels of a plurality of subchannels such that a number of subchannels that are to modulate data bit signals from more than one error correction symbol during a transmission period is reduced or minimized.

61. The multicarrier modulation system of claim 60, wherein the processor is further configured to cause the transceiver to transmit the plurality of data bit signals over the plurality of subchannels, including transmission of fewer than the predetermined number of data bit signals over at least one of the plurality of subchannels.

62. The multicarrier modulation system of claim 60, wherein the processor is further configured to group the plurality of subchannels into groups comprised of one or more subchannels based on a number of data bit signals modulable over each of the plurality of subchannels.

63. The multicarrier modulation system of claim 60, wherein the processor is further configured to determine a subchannel order in which to allocate the plurality of data bit signals to the subchannels.

64. The multicarrier modulation system of claim 63, wherein the subchannel order is based upon a bit size of the plurality of error correction symbols and a number of data bit signals modulable over each of the plurality of subchannels.

65. The multicarrier modulation system of claim 60, wherein the processor is further configured to adjust a number of data bit signals modulable over a given subchannel to reduce or minimize the number of subchannels that modulate data bit signals from more than one error correction symbol during a transmission period.

66. The multicarrier modulation system of claim 65, wherein the processor is further configured to adjust a transmission gain for the given subchannel.

67. The multicarrier modulation system of claim 65, wherein the processor is further configured to adjust a signal-to-noise ratio for the given subchannel.

68. A computer-readable memory, comprising stored computer-executable program instructions configured to cause an apparatus, in response to execution of the program instructions by the apparatus, to perform operations comprising:

transmitting a plurality of data bit signals of a serial input data stream over a plurality of carrier signals, wherein subsets of the plurality of data bit signals comprise error correction symbols, and wherein a number of data bit signals modulable on at least one carrier signal is fewer than a bit size of a one of the error correction symbols; and

allocating the plurality of data bit signals among the plurality of carrier signals, such that a number of carrier signals that are to modulate data bit signals belonging to different error correction symbols during a transmission period is accounted for.

69. The computer-readable memory of claim 68, wherein the operations further comprise performing an adjustment of a signal-to-noise margin of at least one channel.

70. The computer-readable memory of claim 69, wherein a signal-to-noise ratio (SNR) of the at the least one channel is approximately or exactly equal to a sum of the SNR margin and a minimum required SNR for the at least one channel, wherein data bit signals to be transmitted via the at least one channel belong to more than one error correction symbol during the transmission period, and wherein the operations further comprise performing the adjustment by increasing the SNR margin so as to reduce a number of data bit signals transmittable by the at least one channel at a predetermined bit error rate probability.

71. The computer-readable memory of claim 69, wherein the operations further comprise performing the adjustment by an assignment, to the at least one channel, of data bit signals from only a single error correction symbol for a transmission period.

72. The computer-readable memory of claim 68, wherein the operations further comprise reducing the number of carrier signals that are to modulate data bits signals belonging to different error correction symbols during a transmission period.

73. The computer-readable memory of claim 68, wherein the operations further comprise minimizing the number of carrier signals that modulate data bits signals belonging to different error correction symbols during a transmission period.

74. A computer-readable memory, comprising stored computer-executable program instructions configured to cause an apparatus, in response to execution of the program instructions by the apparatus, to perform operations comprising:

including a predetermined number of data bit signals of an input data stream in each of a plurality of error correction symbols; and

allocating a plurality of data bit signals among groups of subchannels of a plurality of subchannels such that a number of subchannels that are to modulate data bit signals from more than one error correction symbol during a transmission period is reduced or minimized.

75. The computer-readable memory of claim 74, wherein the operations further comprise transmitting the plurality of data bit signals over the plurality of subchannels, including transmission of fewer than the predetermined number of data bit signals over at least one of the plurality of subchannels.

76. The computer-readable memory of claim 74, wherein the operations further comprise grouping the plurality of subchannels into groups comprised of one or more subchannels based on a number of data bit signals modulable over the subchannels.

77. The computer-readable memory of claim 74, wherein the operations further comprise determining a subchannel order in which to allocate the plurality of data bit signals to the subchannels.

78. The computer-readable medium of claim 77, wherein the subchannel order is based upon a bit size of the plurality of error correction symbols and numbers of data bit signals modulable over each of the plurality of subchannels.

79. The computer-readable memory of claim 74, wherein the operations further comprise adjusting a number of data bit signals modulable over a given subchannel to reduce or minimize the number of subchannels that modulate data bit signals from more than one error correction symbol during a transmission period.

80. The computer-readable memory of claim 79, wherein the operations further comprise adjusting a transmission gain for the given subchannel.

81. The computer-readable memory of claim 79, wherein the operations further comprise adjusting a signal-to-noise ratio for the given subchannel.